From patchwork Tue May 12 07:03:02 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 471154 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id ECD6B1400A0 for ; Tue, 12 May 2015 17:03:12 +1000 (AEST) Received: from ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id D5DBA1A024F for ; Tue, 12 May 2015 17:03:12 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id CB09B1A0145 for ; Tue, 12 May 2015 17:03:07 +1000 (AEST) Received: from localhost (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id t4C733D9011992 for ; Tue, 12 May 2015 02:03:04 -0500 Message-ID: <1431414182.20218.27.camel@kernel.crashing.org> From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Tue, 12 May 2015 17:03:02 +1000 X-Mailer: Evolution 3.12.11-0ubuntu3 Mime-Version: 1.0 Subject: [Skiboot] [PATCH 1/2] Add a couple more missing Naples references X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The i2c and SLW code are testing for P8 chips by chip type and missing Naples. Fix this. Signed-off-by: Benjamin Herrenschmidt --- hw/p8-i2c.c | 2 ++ hw/slw.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/p8-i2c.c b/hw/p8-i2c.c index 52b9489..f1bddc7 100644 --- a/hw/p8-i2c.c +++ b/hw/p8-i2c.c @@ -288,6 +288,8 @@ static bool p8_i2c_has_irqs(void) return chip->ec_level >= 0x21; case PROC_CHIP_P8_VENICE: return chip->ec_level >= 0x20; + case PROC_CHIP_P8_NAPLES: + return true; default: return false; } diff --git a/hw/slw.c b/hw/slw.c index ffa9de1..d4b648c 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -537,7 +537,8 @@ static void add_cpu_idle_state_properties(void) chip = next_chip(NULL); assert(chip); if (chip->type == PROC_CHIP_P8_MURANO || - chip->type == PROC_CHIP_P8_VENICE) { + chip->type == PROC_CHIP_P8_VENICE || + chip->type == PROC_CHIP_P8_NAPLES) { const struct dt_property *p; p = dt_find_property(dt_root, "ibm,enabled-idle-states");