From patchwork Thu Apr 9 05:08:28 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 459580 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 846C01401E7 for ; Thu, 9 Apr 2015 15:08:39 +1000 (AEST) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 686FD1A086D for ; Thu, 9 Apr 2015 15:08:39 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 0819B1A0571 for ; Thu, 9 Apr 2015 15:08:33 +1000 (AEST) Received: from localhost (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.13.8) with ESMTP id t3958TUP000369 for ; Thu, 9 Apr 2015 00:08:30 -0500 Message-ID: <1428556108.18187.57.camel@kernel.crashing.org> From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 09 Apr 2015 15:08:28 +1000 X-Mailer: Evolution 3.12.10-0ubuntu1~14.10.1 Mime-Version: 1.0 Subject: [Skiboot] [PATCH] phb3: Add Naples PHB support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This detects the new PHB revision and does the appropriate updates to the init sequence. Signed-off-by: Benjamin Herrenschmidt --- hw/phb3.c | 39 +++++++++++++++++++++++---------------- include/phb3-regs.h | 2 ++ include/phb3.h | 1 + 3 files changed, 26 insertions(+), 16 deletions(-) diff --git a/hw/phb3.c b/hw/phb3.c index dfa49fa..51e5679 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -3497,7 +3497,9 @@ static void phb3_init_ioda2(struct phb3 *p) /* Init_24 - Interrupt represent timers * The register doesn't take effect on Murano DD1.0 */ - if (p->rev >= PHB3_REV_MURANO_DD20) + if (p->rev >= PHB3_REV_NAPLES_DD10) + out_be64(p->regs + PHB_INTREP_TIMER, 0x0014000000000000); + else if (p->rev >= PHB3_REV_MURANO_DD20) out_be64(p->regs + PHB_INTREP_TIMER, 0x0004000000000000); else out_be64(p->regs + PHB_INTREP_TIMER, 0); @@ -3703,10 +3705,8 @@ static void phb3_init_utl(struct phb3 *p) /* Init_80..81: Setup tag allocations * - * Don't touch UTL_GBIF_READ_TAGS_ALLOC, it differs betwen PHBs - * and the default is correct + * Stick to HW defaults. May differs between PHB implementations */ - out_be64(p->regs + UTL_PCIE_TAGS_ALLOC, 0x0800000000000000); /* Init_82: PCI Express port control * SW283991: Set Outbound Non-Posted request timeout to 16ms (RTOS). @@ -3856,18 +3856,16 @@ static void phb3_init_hw(struct phb3 *p) /* Init_8 - PCIE System Configuration Register * - * Not changed from default values. Beware that bits [04:09] should - * be different between PHBs (x16 vs x8). + * Use default values, clear bit 15 (SYS_EC00_SLOT) to avoid incorrect + * slot power limit message and adjust max speed based on system + * config. Don't hard wire default value as some bits are different + * between implementations. */ - PHBDBG(p, "Default system config: 0x%016llx\n", - in_be64(p->regs + PHB_PCIE_SYSTEM_CONFIG)); - if (p->index == 2) - val = 0x421000fc00000000; - else - val = 0x441000fc00000000; - val |= (uint64_t)p->max_link_speed << PPC_BITLSHIFT(35); + val = in_be64(p->regs + PHB_PCIE_SYSTEM_CONFIG); + PHBDBG(p, "Default system config: 0x%016llx\n", val); + val = SETFIELD(PHB_PCIE_SCONF_SLOT, val, 0); + val = SETFIELD(PHB_PCIE_SCONF_MAXLINKSPEED, val, p->max_link_speed); out_be64(p->regs + PHB_PCIE_SYSTEM_CONFIG, val); - PHBDBG(p, "New system config : 0x%016llx\n", in_be64(p->regs + PHB_PCIE_SYSTEM_CONFIG)); @@ -3886,9 +3884,10 @@ static void phb3_init_hw(struct phb3 *p) /* Init_XX - (PHB2 errata) * * Set proper credits, needs adjustment due to wrong defaults - * on PHB2 before we lift the reset. + * on PHB2 before we lift the reset. This only applies to Murano + * and Venice */ - if (p->index == 2) + if (p->index == 2 && p->rev < PHB3_REV_NAPLES_DD10) out_be64(p->regs + PHB_PCIE_SYS_LINK_INIT, 0x9008133332120000); /* Init_13 - PCIE Reset */ @@ -3935,6 +3934,14 @@ static void phb3_init_hw(struct phb3 *p) #endif if (p->rev >= PHB3_REV_MURANO_DD20) val |= 0x0000010000000000; + if (p->rev >= PHB3_REV_NAPLES_DD10) { + /* Enable 32-bit bypass support on Naples and tell the OS + * about it + */ + val |= 0x0010000000000000; + dt_add_property(p->phb.dt_node, + "ibm,32-bit-bypass-supported", NULL, 0); + } out_be64(p->regs + PHB_CONTROL, val); /* Init_88..128 : Setup error registers */ diff --git a/include/phb3-regs.h b/include/phb3-regs.h index b3f7160..632ed93 100644 --- a/include/phb3-regs.h +++ b/include/phb3-regs.h @@ -169,6 +169,8 @@ /* PCI-E Stack registers */ #define PHB_PCIE_SYSTEM_CONFIG 0x600 +#define PHB_PCIE_SCONF_SLOT PPC_BIT(15) +#define PHB_PCIE_SCONF_MAXLINKSPEED PPC_BITMASK(32,35) #define PHB_PCIE_BUS_NUMBER 0x608 #define PHB_PCIE_SYSTEM_TEST 0x618 #define PHB_PCIE_LINK_MANAGEMENT 0x630 diff --git a/include/phb3.h b/include/phb3.h index 6276f1a..3db57ad 100644 --- a/include/phb3.h +++ b/include/phb3.h @@ -270,6 +270,7 @@ struct phb3 { #define PHB3_REV_MURANO_DD20 0xa30003 #define PHB3_REV_MURANO_DD21 0xa30004 #define PHB3_REV_VENICE_DD20 0xa30005 +#define PHB3_REV_NAPLES_DD10 0xb30001 void *regs; uint64_t pe_xscom; /* XSCOM bases */ uint64_t pci_xscom;