From patchwork Tue Mar 31 09:47:35 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frederic Barrat X-Patchwork-Id: 1264624 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 48s4Kk40S2z9sSl for ; Tue, 31 Mar 2020 20:49:14 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 48s4Kj2LgbzDr1D for ; Tue, 31 Mar 2020 20:49:13 +1100 (AEDT) X-Original-To: skiboot-stable@lists.ozlabs.org Delivered-To: skiboot-stable@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0b-001b2d01.pphosted.com; envelope-from=fbarrat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 48s4Jk2rQwzDr0D for ; Tue, 31 Mar 2020 20:48:21 +1100 (AEDT) Received: from pps.filterd (m0127361.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 02V9Y1th151066 for ; Tue, 31 Mar 2020 05:48:19 -0400 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 303ymjxaff-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 31 Mar 2020 05:48:19 -0400 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 31 Mar 2020 10:48:02 +0100 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 02V9mC1b58458298 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 31 Mar 2020 09:48:12 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 3302FAE056; Tue, 31 Mar 2020 09:48:12 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E6A7EAE04D; Tue, 31 Mar 2020 09:48:11 +0000 (GMT) Received: from pic2.home (unknown [9.145.78.7]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 31 Mar 2020 09:48:11 +0000 (GMT) From: Frederic Barrat To: skiboot@lists.ozlabs.org Date: Tue, 31 Mar 2020 11:47:35 +0200 X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200331094735.82874-1-fbarrat@linux.ibm.com> References: <20200331094735.82874-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 20033109-0016-0000-0000-000002FB8DDE X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20033109-0017-0000-0000-0000335F4C46 Message-Id: <20200331094735.82874-2-fbarrat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-03-31_03:2020-03-30, 2020-03-31 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 suspectscore=1 adultscore=0 malwarescore=0 impostorscore=0 priorityscore=1501 clxscore=1015 phishscore=0 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2003310081 Subject: [Skiboot-stable] [PATCH 2/2] platform/mihawk: Tune equalization settings for opencapi X-BeenThere: skiboot-stable@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: "Patches, review, and discussion for stable releases of skiboot" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: clombard@linux.ibm.com, skiboot-stable@lists.ozlabs.org, chhank@tw.ibm.com, andrew.donnellan@au1.ibm.com, joy_chu@wistron.com Errors-To: skiboot-stable-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot-stable" The Bittware 250SOC adapter on Mihawk was showing a high count of CRC errors on one of the opencapi slots. The PHY team suggested new equalization settings to correct the errors. All existing adapters have been tested on mihawk to make sure the settings are compatible. However, the new settings should not be used on platforms other than mihawk. The changes specific to mihawk are: - Update the tx_ffe_pre_coeff and tx_ffe_post_coeff input parameters used during zcal - turn off the tx_ffe_boost parameter through scom Signed-off-by: Frederic Barrat Cc: skiboot-stable@lists.ozlabs.org # skiboot-op940.x --- hw/npu2-hw-procedures.c | 25 ++++++++++++++++++------- include/npu2.h | 2 ++ platforms/astbmc/mihawk.c | 1 + 3 files changed, 21 insertions(+), 7 deletions(-) diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 890b25a8..95a0f9dc 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -78,6 +78,7 @@ static struct npu2_phy_reg NPU2_PHY_TX_ZCAL_DONE = {0x3c1, 50, 1}; static struct npu2_phy_reg NPU2_PHY_TX_ZCAL_ERROR = {0x3c1, 51, 1}; static struct npu2_phy_reg NPU2_PHY_TX_ZCAL_N = {0x3c3, 48, 9}; static struct npu2_phy_reg NPU2_PHY_TX_ZCAL_P = {0x3c5, 48, 9}; +static struct npu2_phy_reg NPU2_PHY_TX_FFE_BOOST_EN = {0x34b, 59, 1}; static struct npu2_phy_reg NPU2_PHY_TX_PSEG_PRE_EN = {0x34d, 51, 5}; static struct npu2_phy_reg NPU2_PHY_TX_PSEG_PRE_SELECT = {0x34d, 56, 5}; static struct npu2_phy_reg NPU2_PHY_TX_NSEG_PRE_EN = {0x34f, 51, 5}; @@ -498,10 +499,11 @@ static uint32_t phy_tx_zcal_wait(struct npu2_dev *ndev) return PROCEDURE_NEXT; } -#define MARGIN_RATIO (0) -#define FFE_PRE_COEFF (0) -#define FFE_POST_COEFF (0) +int ffe_pre_coeff = 0; +int ffe_post_coeff = 0; + +#define MARGIN_RATIO (0) #define PRE_WIDTH (5) #define POST_WIDTH (7) #define MAIN_WIDTH (7) @@ -565,8 +567,8 @@ static uint32_t phy_tx_zcal_calculate(struct npu2_dev *ndev) return PROCEDURE_COMPLETE | PROCEDURE_FAILED; p_value = zcal_p - TOTAL_X2_MAX; - p_precursor_select = (p_value * FFE_PRE_COEFF)/128; - p_postcursor_select = (p_value * FFE_POST_COEFF)/128; + p_precursor_select = (p_value * ffe_pre_coeff)/128; + p_postcursor_select = (p_value * ffe_post_coeff)/128; margin_pu_select = (p_value * MARGIN_RATIO)/256; if (p_value % 2) { @@ -587,8 +589,8 @@ static uint32_t phy_tx_zcal_calculate(struct npu2_dev *ndev) } n_value = zcal_n - TOTAL_X2_MAX; - n_precursor_select = (n_value * FFE_PRE_COEFF)/128; - n_postcursor_select = (n_value * FFE_POST_COEFF)/128; + n_precursor_select = (n_value * ffe_pre_coeff)/128; + n_postcursor_select = (n_value * ffe_post_coeff)/128; margin_pd_select = (p_value * MARGIN_RATIO)/256; if (n_value % 2) { @@ -1065,3 +1067,12 @@ void npu2_opencapi_phy_prbs31(struct npu2_dev *dev) { phy_write(dev, &NPU2_PHY_TX_DRV_DATA_PATTERN_GCRMSG, 0xD); } + +void mihawk_phy_setup(struct npu2_dev *dev) +{ + /* Tune equalization settings */ + NPU2DEVINF(dev, "Enabling Mihawk-specific PHY setup\n"); + phy_write(dev, &NPU2_PHY_TX_FFE_BOOST_EN, 0); + ffe_pre_coeff = 0x3; + ffe_post_coeff = 0x14; +} diff --git a/include/npu2.h b/include/npu2.h index eb7c4558..cab1e7ac 100644 --- a/include/npu2.h +++ b/include/npu2.h @@ -243,6 +243,8 @@ int64_t npu2_freeze_status(struct phb *phb __unused, uint16_t *severity __unused); void npu2_dump_scoms(int chip_id); +void mihawk_phy_setup(struct npu2_dev *dev); + int64_t npu2_init_context(struct phb *phb, uint64_t msr, uint64_t bdf); int64_t npu2_destroy_context(struct phb *phb, uint64_t bdf); int64_t npu2_map_lpar(struct phb *phb, uint64_t bdf, uint64_t lparid, diff --git a/platforms/astbmc/mihawk.c b/platforms/astbmc/mihawk.c index 8971b407..813ab406 100644 --- a/platforms/astbmc/mihawk.c +++ b/platforms/astbmc/mihawk.c @@ -157,6 +157,7 @@ static const struct platform_ocapi mihawk_ocapi = { .i2c_presence_brick5 = 0, /* unused */ .odl_phy_swap = true, .ocapi_slot_label = mihawk_ocapi_slot_label, + .phy_setup = mihawk_phy_setup, }; static const struct slot_table_entry P1E1A_x8_PLX8748_RiserA_down[] = {