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[109.148.232.11]) by mx.google.com with ESMTPSA id y67sm5772300yhc.11.2014.12.15.03.26.07 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 15 Dec 2014 03:26:09 -0800 (PST) From: Lee Jones To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: lee.jones@linaro.org, kernel@stlinux.com, a.zummo@towertech.it, rtc-linux@googlegroups.com, wim@iguana.be, linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, David Paris Subject: [rtc-linux] [PATCH 8/8] ARM: STi: DT: STiH407: Add Device Tree node for the LPC Date: Mon, 15 Dec 2014 11:25:38 +0000 Message-Id: <1418642738-17407-9-git-send-email-lee.jones@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1418642738-17407-1-git-send-email-lee.jones@linaro.org> References: <1418642738-17407-1-git-send-email-lee.jones@linaro.org> X-Original-Sender: lee.jones@linaro.org X-Original-Authentication-Results: gmr-mx.google.com; spf=pass (google.com: domain of lee.jones@linaro.org designates 209.85.213.41 as permitted sender) smtp.mail=lee.jones@linaro.org Reply-To: rtc-linux@googlegroups.com Precedence: list Mailing-list: list rtc-linux@googlegroups.com; contact rtc-linux+owners@googlegroups.com List-ID: X-Google-Group-Id: 712029733259 List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , On current ST platforms the LPC controls a number of functions. This patch enables support for the LPC Watchdog and LPC RTC devices on LPC1 and LPC2 respectively. Signed-off-by: David Paris Signed-off-by: Lee Jones --- arch/arm/boot/dts/stih407.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi index f539627a..a2bba83 100644 --- a/arch/arm/boot/dts/stih407.dtsi +++ b/arch/arm/boot/dts/stih407.dtsi @@ -8,6 +8,7 @@ */ #include "stih407-clock.dtsi" #include "stih407-pinctrl.dtsi" +#include / { #address-cells = <1>; #size-cells = <1>; @@ -259,5 +260,24 @@ status = "disabled"; }; + + /* Watchdog and Real-Time Clock */ + lpc@8787000 { + compatible = "st,stih407-lpc"; + reg = <0x8787000 0x1000>; + interrupts = ; + clocks = <&clk_s_d3_flexgen CLK_LPC_0>; + timeout-sec = <600>; + st,syscfg = <&syscfg_core>; + st,lpc-mode = ; + }; + + lpc@8788000 { + compatible = "st,stih407-lpc"; + reg = <0x8788000 0x1000>; + interrupts = ; + clocks = <&clk_s_d3_flexgen CLK_LPC_1>; + st,lpc-mode = ; + }; }; };