From patchwork Tue Feb 27 15:08:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: BALATON Zoltan X-Patchwork-Id: 1905214 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=patchwork.ozlabs.org) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4TkgqJ3SZYz1yX4 for ; Wed, 28 Feb 2024 02:08:44 +1100 (AEDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rez4C-0003M7-Dy; Tue, 27 Feb 2024 10:08:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rez4A-0003Jr-2K; Tue, 27 Feb 2024 10:08:22 -0500 Received: from zero.eik.bme.hu ([152.66.115.2]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1rez45-00081O-3H; Tue, 27 Feb 2024 10:08:21 -0500 Received: from zero.eik.bme.hu (localhost [127.0.0.1]) by zero.eik.bme.hu (Postfix) with ESMTP id B711D4E60D2; Tue, 27 Feb 2024 16:08:07 +0100 (CET) X-Virus-Scanned: amavisd-new at eik.bme.hu Received: from zero.eik.bme.hu ([127.0.0.1]) by zero.eik.bme.hu (zero.eik.bme.hu [127.0.0.1]) (amavisd-new, port 10028) with ESMTP id DPn0BUGaNH8d; Tue, 27 Feb 2024 16:08:05 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id C9E744E60D5; Tue, 27 Feb 2024 16:08:05 +0100 (CET) Message-Id: <4c813b27498fac293b1284f78bdbb6b94286f3c3.1709045654.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Subject: [PATCH v7 05/10] target/ppc: Move patching nip from exception handler to helper_scv MIME-Version: 1.0 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Cc: Nicholas Piggin , Daniel Henrique Barboza , clg@kaod.org Date: Tue, 27 Feb 2024 16:08:05 +0100 (CET) Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Nicholas Piggin Unlike sc, for scv a facility unavailable interrupt must be generated if FSCR[SCV]=0 so we can't raise the exception with nip set to next instruction but we can move advancing nip if the FSCR check passes to helper_scv so the exception handler does not need to change it. [balaton: added commit message] Signed-off-by: BALATON Zoltan --- target/ppc/excp_helper.c | 2 +- target/ppc/translate.c | 6 +++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index f1e62d9878..6cf4542e7e 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1414,7 +1414,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) case POWERPC_EXCP_SYSCALL_VECTORED: /* scv exception */ lev = env->error_code; dump_syscall(env); - env->nip += 4; new_msr |= env->msr & ((target_ulong)1 << MSR_EE); new_msr |= env->msr & ((target_ulong)1 << MSR_RI); @@ -2537,6 +2536,7 @@ void helper_ppc_maybe_interrupt(CPUPPCState *env) void helper_scv(CPUPPCState *env, uint32_t lev) { if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) { + env->nip += 4; raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev); } else { raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index a3ac8c3d0e..1d69283c80 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4590,7 +4590,11 @@ static void gen_scv(DisasContext *ctx) { uint32_t lev = (ctx->opcode >> 5) & 0x7F; - /* Set the PC back to the faulting instruction. */ + /* + * Set the PC back to the scv instruction (unlike sc), because a facility + * unavailable interrupt must be generated if FSCR[SCV]=0. The helper + * advances nip if the FSCR check passes. + */ gen_update_nip(ctx, ctx->cia); gen_helper_scv(tcg_env, tcg_constant_i32(lev));