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[217.237.127.109]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9e5664350esm424328866b.159.2024.11.03.05.34.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2024 05:34:53 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Jason Wang , qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9?= =?utf-8?q?dric_Le_Goater?= , Paolo Bonzini , Hanna Reitz , Nicholas Piggin , Corey Minyard , Kevin Wolf , Bin Meng , =?utf-8?q?Phi?= =?utf-8?q?lippe_Mathieu-Daud=C3=A9?= , Bernhard Beschow , qemu-block@nongnu.org, Alex Williamson , Daniel Henrique Barboza Subject: [PATCH v4 09/26] hw/ppc/ppce500_ccsr: Trace access to CCSR region Date: Sun, 3 Nov 2024 14:33:55 +0100 Message-ID: <20241103133412.73536-10-shentey@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241103133412.73536-1-shentey@gmail.com> References: <20241103133412.73536-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org The CCSR space is just a container which is meant to be covered by platform device memory regions. However, QEMU only implements a subset of these devices. Add some tracing to see which unimplemented devices a guest attempts to access. Signed-off-by: Bernhard Beschow --- hw/ppc/ppce500_ccsr.c | 25 ++++++++++++++++++++++++- hw/ppc/trace-events | 3 +++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/hw/ppc/ppce500_ccsr.c b/hw/ppc/ppce500_ccsr.c index b1fb4090c0..31efc7bee8 100644 --- a/hw/ppc/ppce500_ccsr.c +++ b/hw/ppc/ppce500_ccsr.c @@ -13,12 +13,35 @@ #include "qemu/osdep.h" #include "ppce500_ccsr.h" +#include "trace.h" + +static uint64_t ppce500_ccsr_io_read(void *opaque, hwaddr addr, unsigned size) +{ + uint64_t value = 0; + + trace_ppce500_ccsr_io_read(addr, value, size); + + return value; +} + +static void ppce500_ccsr_io_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + trace_ppce500_ccsr_io_write(addr, value, size); +} + +static const MemoryRegionOps ppce500_ccsr_ops = { + .read = ppce500_ccsr_io_read, + .write = ppce500_ccsr_io_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; static void ppce500_ccsr_init(Object *obj) { PPCE500CCSRState *s = CCSR(obj); - memory_region_init(&s->ccsr_space, obj, "e500-ccsr", MPC85XX_CCSRBAR_SIZE); + memory_region_init_io(&s->ccsr_space, obj, &ppce500_ccsr_ops, obj, + "e500-ccsr", MPC85XX_CCSRBAR_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->ccsr_space); } diff --git a/hw/ppc/trace-events b/hw/ppc/trace-events index 1f125ce841..ca4c231c9f 100644 --- a/hw/ppc/trace-events +++ b/hw/ppc/trace-events @@ -143,6 +143,9 @@ ppc_irq_cpu(const char *action) "%s" ppc_dcr_read(uint32_t addr, uint32_t val) "DRCN[0x%x] -> 0x%x" ppc_dcr_write(uint32_t addr, uint32_t val) "DRCN[0x%x] <- 0x%x" +ppce500_ccsr_io_read(uint32_t index, uint32_t val, uint8_t size) "[0x%" PRIx32 "] -> 0x%08x (size: 0x%" PRIu8 ")" +ppce500_ccsr_io_write(uint32_t index, uint32_t val, uint8_t size) "[0x%" PRIx32 "] <- 0x%08x (size: 0x%" PRIu8 ")" + # prep_systemio.c prep_systemio_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x" prep_systemio_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x"