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[217.237.127.109]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9e5664350esm307859066b.159.2024.11.02.06.17.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 02 Nov 2024 06:17:29 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Nicholas Piggin , qemu-block@nongnu.org, Bin Meng , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Jason Wang , Bernhard Beschow , Daniel Henrique Barboza , Kevin Wolf , Hanna Reitz , =?utf-8?q?C?= =?utf-8?q?=C3=A9dric_Le_Goater?= , Alex Williamson , qemu-ppc@nongnu.org, Corey Minyard Subject: [PATCH v3 01/26] hw/ppc/e500: Do not leak struct boot_info Date: Sat, 2 Nov 2024 14:16:50 +0100 Message-ID: <20241102131715.548849-2-shentey@gmail.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20241102131715.548849-1-shentey@gmail.com> References: <20241102131715.548849-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=shentey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org The struct is allocated once with g_new0() but never free()'d. Fix the leakage by adding an attribute to struct PPCE500MachineState which avoids the allocation. While at it remove the obsolete /*< private >*/ markers. Signed-off-by: Bernhard Beschow --- hw/ppc/e500.h | 9 +++++++-- hw/ppc/e500.c | 17 ++++------------- 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h index 8c09ef92e4..4a1b42d44b 100644 --- a/hw/ppc/e500.h +++ b/hw/ppc/e500.h @@ -5,18 +5,23 @@ #include "hw/platform-bus.h" #include "qom/object.h" +struct boot_info { + uint32_t dt_base; + uint32_t dt_size; + uint32_t entry; +}; + struct PPCE500MachineState { - /*< private >*/ MachineState parent_obj; /* points to instance of TYPE_PLATFORM_BUS_DEVICE if * board supports dynamic sysbus devices */ PlatformBusDevice *pbus_dev; + struct boot_info boot_info; }; struct PPCE500MachineClass { - /*< private >*/ MachineClass parent_class; /* required -- must at least add toplevel board compatible */ diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index b760c6d6a2..ba83f33033 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -80,13 +80,6 @@ #define PLATFORM_CLK_FREQ_HZ (400 * 1000 * 1000) -struct boot_info -{ - uint32_t dt_base; - uint32_t dt_size; - uint32_t entry; -}; - static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot, int nr_slots, int *len) { @@ -919,7 +912,6 @@ void ppce500_init(MachineState *machine) bool kernel_as_payload; hwaddr bios_entry = 0; target_long payload_size; - struct boot_info *boot_info = NULL; int dt_size; int i; unsigned int smp_cpus = machine->smp.cpus; @@ -974,9 +966,8 @@ void ppce500_init(MachineState *machine) /* Register reset handler */ if (!i) { /* Primary CPU */ - boot_info = g_new0(struct boot_info, 1); qemu_register_reset(ppce500_cpu_reset, cpu); - env->load_info = boot_info; + env->load_info = &pms->boot_info; } else { /* Secondary CPUs */ qemu_register_reset(ppce500_cpu_reset_sec, cpu); @@ -1274,9 +1265,9 @@ void ppce500_init(MachineState *machine) } assert(dt_size < DTB_MAX_SIZE); - boot_info->entry = bios_entry; - boot_info->dt_base = dt_base; - boot_info->dt_size = dt_size; + pms->boot_info.entry = bios_entry; + pms->boot_info.dt_base = dt_base; + pms->boot_info.dt_size = dt_size; } static void e500_ccsr_initfn(Object *obj)