@@ -13,12 +13,35 @@
#include "qemu/osdep.h"
#include "ppce500_ccsr.h"
+#include "trace.h"
+
+static uint64_t ppce500_ccsr_io_read(void *opaque, hwaddr addr, unsigned size)
+{
+ uint64_t value = 0;
+
+ trace_ppce500_ccsr_io_read(addr, value, size);
+
+ return value;
+}
+
+static void ppce500_ccsr_io_write(void *opaque, hwaddr addr, uint64_t value,
+ unsigned size)
+{
+ trace_ppce500_ccsr_io_write(addr, value, size);
+}
+
+static const MemoryRegionOps ppce500_ccsr_ops = {
+ .read = ppce500_ccsr_io_read,
+ .write = ppce500_ccsr_io_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
static void ppce500_ccsr_init(Object *obj)
{
PPCE500CCSRState *s = CCSR(obj);
- memory_region_init(&s->ccsr_space, obj, "e500-ccsr", MPC85XX_CCSRBAR_SIZE);
+ memory_region_init_io(&s->ccsr_space, obj, &ppce500_ccsr_ops, obj,
+ "e500-ccsr", MPC85XX_CCSRBAR_SIZE);
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->ccsr_space);
}
@@ -143,6 +143,9 @@ ppc_irq_cpu(const char *action) "%s"
ppc_dcr_read(uint32_t addr, uint32_t val) "DRCN[0x%x] -> 0x%x"
ppc_dcr_write(uint32_t addr, uint32_t val) "DRCN[0x%x] <- 0x%x"
+ppce500_ccsr_io_read(uint32_t index, uint32_t val, uint8_t size) "[0x%" PRIx32 "] -> 0x%08x (size: 0x%" PRIu8 ")"
+ppce500_ccsr_io_write(uint32_t index, uint32_t val, uint8_t size) "[0x%" PRIx32 "] <- 0x%08x (size: 0x%" PRIu8 ")"
+
# prep_systemio.c
prep_systemio_read(uint32_t addr, uint32_t val) "read addr=0x%x val=0x%x"
prep_systemio_write(uint32_t addr, uint32_t val) "write addr=0x%x val=0x%x"
The CCSR space is just a container which is meant to be covered by platform device memory regions. However, QEMU only implements a subset of these devices. Add some tracing to see which unimplemented devices a guest attempts to access. Signed-off-by: Bernhard Beschow <shentey@gmail.com> --- hw/ppc/ppce500_ccsr.c | 25 ++++++++++++++++++++++++- hw/ppc/trace-events | 3 +++ 2 files changed, 27 insertions(+), 1 deletion(-)