| Message ID | 20240913041337.912876-7-harshpb@linux.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | misc ppc improvements/optimizations | expand |
On Fri Sep 13, 2024 at 2:13 PM AEST, Harsh Prateek Bora wrote: > Historically, the registration of sprs have been inherited alongwith > every new Power arch support being added leading to a lot of code > duplication. It's time to do necessary cleanups now to avoid further > duplication with newer arch support being added. Looks okay. Reviewed-by: Nicholas Piggin <npiggin@gmail.com> Nit, could you move this out to the end of the series, since it is in the middle of several other patches that deal with interrupt delivery. Thanks, Nick > > Signed-off-by: Harsh Prateek Bora <harshb@linux.ibm.com> > --- > target/ppc/cpu_init.c | 58 +++++++++---------------------------------- > 1 file changed, 12 insertions(+), 46 deletions(-) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 9cb5dd4596..de1dd63bf7 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -6410,7 +6410,7 @@ static struct ppc_radix_page_info POWER9_radix_page_info = { > #endif /* CONFIG_USER_ONLY */ > > #define POWER9_BHRB_ENTRIES_LOG2 5 > -static void init_proc_POWER9(CPUPPCState *env) > +static void register_power9_common_sprs(CPUPPCState *env) > { > /* Common Registers */ > init_proc_book3s_common(env); > @@ -6429,7 +6429,6 @@ static void init_proc_POWER9(CPUPPCState *env) > register_power5p_ear_sprs(env); > register_power5p_tb_sprs(env); > register_power6_common_sprs(env); > - register_HEIR32_spr(env); > register_power6_dbg_sprs(env); > register_power7_common_sprs(env); > register_power8_tce_address_control_sprs(env); > @@ -6447,16 +6446,21 @@ static void init_proc_POWER9(CPUPPCState *env) > register_power8_rpr_sprs(env); > register_power9_mmu_sprs(env); > > - /* POWER9 Specific registers */ > - spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, > - spr_read_generic, spr_write_generic, > - KVM_REG_PPC_TIDR, 0); > - > /* FIXME: Filter fields properly based on privilege level */ > spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, > spr_read_generic, spr_write_generic, > KVM_REG_PPC_PSSCR, 0); > > +} > + > +static void init_proc_POWER9(CPUPPCState *env) > +{ > + register_power9_common_sprs(env); > + register_HEIR32_spr(env); > + /* POWER9 Specific registers */ > + spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, > + spr_read_generic, spr_write_generic, > + KVM_REG_PPC_TIDR, 0); > /* env variables */ > env->dcache_line_size = 128; > env->icache_line_size = 128; > @@ -6562,50 +6566,12 @@ static struct ppc_radix_page_info POWER10_radix_page_info = { > #define POWER10_BHRB_ENTRIES_LOG2 5 > static void init_proc_POWER10(CPUPPCState *env) > { > - /* Common Registers */ > - init_proc_book3s_common(env); > - register_book3s_207_dbg_sprs(env); > - > - /* Common TCG PMU */ > - init_tcg_pmu_power8(env); > - > - /* POWER8 Specific Registers */ > - register_book3s_ids_sprs(env); > - register_amr_sprs(env); > - register_iamr_sprs(env); > - register_book3s_purr_sprs(env); > - register_power5p_common_sprs(env); > - register_power5p_lpar_sprs(env); > - register_power5p_ear_sprs(env); > - register_power5p_tb_sprs(env); > - register_power6_common_sprs(env); > + register_power9_common_sprs(env); > register_HEIR64_spr(env); > - register_power6_dbg_sprs(env); > - register_power7_common_sprs(env); > - register_power8_tce_address_control_sprs(env); > - register_power8_ids_sprs(env); > - register_power8_ebb_sprs(env); > - register_power8_fscr_sprs(env); > - register_power8_pmu_sup_sprs(env); > - register_power8_pmu_user_sprs(env); > - register_power8_tm_sprs(env); > - register_power8_pspb_sprs(env); > - register_power8_dpdes_sprs(env); > - register_vtb_sprs(env); > - register_power8_ic_sprs(env); > - register_power9_book4_sprs(env); > - register_power8_rpr_sprs(env); > - register_power9_mmu_sprs(env); > register_power10_hash_sprs(env); > register_power10_dexcr_sprs(env); > register_power10_pmu_sup_sprs(env); > register_power10_pmu_user_sprs(env); > - > - /* FIXME: Filter fields properly based on privilege level */ > - spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, > - spr_read_generic, spr_write_generic, > - KVM_REG_PPC_PSSCR, 0); > - > /* env variables */ > env->dcache_line_size = 128; > env->icache_line_size = 128;
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 9cb5dd4596..de1dd63bf7 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6410,7 +6410,7 @@ static struct ppc_radix_page_info POWER9_radix_page_info = { #endif /* CONFIG_USER_ONLY */ #define POWER9_BHRB_ENTRIES_LOG2 5 -static void init_proc_POWER9(CPUPPCState *env) +static void register_power9_common_sprs(CPUPPCState *env) { /* Common Registers */ init_proc_book3s_common(env); @@ -6429,7 +6429,6 @@ static void init_proc_POWER9(CPUPPCState *env) register_power5p_ear_sprs(env); register_power5p_tb_sprs(env); register_power6_common_sprs(env); - register_HEIR32_spr(env); register_power6_dbg_sprs(env); register_power7_common_sprs(env); register_power8_tce_address_control_sprs(env); @@ -6447,16 +6446,21 @@ static void init_proc_POWER9(CPUPPCState *env) register_power8_rpr_sprs(env); register_power9_mmu_sprs(env); - /* POWER9 Specific registers */ - spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, - spr_read_generic, spr_write_generic, - KVM_REG_PPC_TIDR, 0); - /* FIXME: Filter fields properly based on privilege level */ spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, spr_read_generic, spr_write_generic, KVM_REG_PPC_PSSCR, 0); +} + +static void init_proc_POWER9(CPUPPCState *env) +{ + register_power9_common_sprs(env); + register_HEIR32_spr(env); + /* POWER9 Specific registers */ + spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, + spr_read_generic, spr_write_generic, + KVM_REG_PPC_TIDR, 0); /* env variables */ env->dcache_line_size = 128; env->icache_line_size = 128; @@ -6562,50 +6566,12 @@ static struct ppc_radix_page_info POWER10_radix_page_info = { #define POWER10_BHRB_ENTRIES_LOG2 5 static void init_proc_POWER10(CPUPPCState *env) { - /* Common Registers */ - init_proc_book3s_common(env); - register_book3s_207_dbg_sprs(env); - - /* Common TCG PMU */ - init_tcg_pmu_power8(env); - - /* POWER8 Specific Registers */ - register_book3s_ids_sprs(env); - register_amr_sprs(env); - register_iamr_sprs(env); - register_book3s_purr_sprs(env); - register_power5p_common_sprs(env); - register_power5p_lpar_sprs(env); - register_power5p_ear_sprs(env); - register_power5p_tb_sprs(env); - register_power6_common_sprs(env); + register_power9_common_sprs(env); register_HEIR64_spr(env); - register_power6_dbg_sprs(env); - register_power7_common_sprs(env); - register_power8_tce_address_control_sprs(env); - register_power8_ids_sprs(env); - register_power8_ebb_sprs(env); - register_power8_fscr_sprs(env); - register_power8_pmu_sup_sprs(env); - register_power8_pmu_user_sprs(env); - register_power8_tm_sprs(env); - register_power8_pspb_sprs(env); - register_power8_dpdes_sprs(env); - register_vtb_sprs(env); - register_power8_ic_sprs(env); - register_power9_book4_sprs(env); - register_power8_rpr_sprs(env); - register_power9_mmu_sprs(env); register_power10_hash_sprs(env); register_power10_dexcr_sprs(env); register_power10_pmu_sup_sprs(env); register_power10_pmu_user_sprs(env); - - /* FIXME: Filter fields properly based on privilege level */ - spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, - spr_read_generic, spr_write_generic, - KVM_REG_PPC_PSSCR, 0); - /* env variables */ env->dcache_line_size = 128; env->icache_line_size = 128;
Historically, the registration of sprs have been inherited alongwith every new Power arch support being added leading to a lot of code duplication. It's time to do necessary cleanups now to avoid further duplication with newer arch support being added. Signed-off-by: Harsh Prateek Bora <harshb@linux.ibm.com> --- target/ppc/cpu_init.c | 58 +++++++++---------------------------------- 1 file changed, 12 insertions(+), 46 deletions(-)