| Message ID | 20240909211038.27440-13-kowal@linux.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | XIVE2 changes for TIMA operations | expand |
On 9/9/24 23:10, Michael Kowal wrote: > From: Glenn Miles <milesg@linux.ibm.com> > > Current code was updating the PIPR inside the xive_tctx_accept() function > instead of the xive_tctx_set_cppr function, which is where the HW would > have it updated. > > Moved the update to the xive_tctx_set_cppr function which required > additional support for pool interrupts. > > Fixes: cdd4de68edb6 ("ppc/xive: notify the CPU when the interrupt priority is more privileged") > Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com> > Signed-off-by: Michael Kowal <kowal@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Thanks, C. > --- > hw/intc/xive.c | 34 ++++++++++++++++++++++++++++++++-- > 1 file changed, 32 insertions(+), 2 deletions(-) > > diff --git a/hw/intc/xive.c b/hw/intc/xive.c > index 5c5c3a2dd6..738eaf624d 100644 > --- a/hw/intc/xive.c > +++ b/hw/intc/xive.c > @@ -89,7 +89,6 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) > > /* Reset the pending buffer bit */ > alt_regs[TM_IPB] &= ~xive_priority_to_ipb(cppr); > - regs[TM_PIPR] = ipb_to_pipr(alt_regs[TM_IPB]); > > /* Drop Exception bit */ > regs[TM_NSR] &= ~mask; > @@ -143,6 +142,8 @@ void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring) > static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) > { > uint8_t *regs = &tctx->regs[ring]; > + uint8_t pipr_min; > + uint8_t ring_min; > > trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, > regs[TM_IPB], regs[TM_PIPR], > @@ -154,8 +155,37 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) > > tctx->regs[ring + TM_CPPR] = cppr; > > + /* > + * Recompute the PIPR based on local pending interrupts. The PHYS > + * ring must take the minimum of both the PHYS and POOL PIPR values. > + */ > + pipr_min = ipb_to_pipr(regs[TM_IPB]); > + ring_min = ring; > + > + /* PHYS updates also depend on POOL values */ > + if (ring == TM_QW3_HV_PHYS) { > + uint8_t *pool_regs = &tctx->regs[TM_QW2_HV_POOL]; > + > + /* POOL values only matter if POOL ctx is valid */ > + if (pool_regs[TM_WORD2] & 0x80) { > + > + uint8_t pool_pipr = ipb_to_pipr(pool_regs[TM_IPB]); > + > + /* > + * Determine highest priority interrupt and > + * remember which ring has it. > + */ > + if (pool_pipr < pipr_min) { > + pipr_min = pool_pipr; > + ring_min = TM_QW2_HV_POOL; > + } > + } > + } > + > + regs[TM_PIPR] = pipr_min; > + > /* CPPR has changed, check if we need to raise a pending exception */ > - xive_tctx_notify(tctx, ring); > + xive_tctx_notify(tctx, ring_min); > } > > void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb)
diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 5c5c3a2dd6..738eaf624d 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -89,7 +89,6 @@ static uint64_t xive_tctx_accept(XiveTCTX *tctx, uint8_t ring) /* Reset the pending buffer bit */ alt_regs[TM_IPB] &= ~xive_priority_to_ipb(cppr); - regs[TM_PIPR] = ipb_to_pipr(alt_regs[TM_IPB]); /* Drop Exception bit */ regs[TM_NSR] &= ~mask; @@ -143,6 +142,8 @@ void xive_tctx_reset_signal(XiveTCTX *tctx, uint8_t ring) static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) { uint8_t *regs = &tctx->regs[ring]; + uint8_t pipr_min; + uint8_t ring_min; trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, regs[TM_IPB], regs[TM_PIPR], @@ -154,8 +155,37 @@ static void xive_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) tctx->regs[ring + TM_CPPR] = cppr; + /* + * Recompute the PIPR based on local pending interrupts. The PHYS + * ring must take the minimum of both the PHYS and POOL PIPR values. + */ + pipr_min = ipb_to_pipr(regs[TM_IPB]); + ring_min = ring; + + /* PHYS updates also depend on POOL values */ + if (ring == TM_QW3_HV_PHYS) { + uint8_t *pool_regs = &tctx->regs[TM_QW2_HV_POOL]; + + /* POOL values only matter if POOL ctx is valid */ + if (pool_regs[TM_WORD2] & 0x80) { + + uint8_t pool_pipr = ipb_to_pipr(pool_regs[TM_IPB]); + + /* + * Determine highest priority interrupt and + * remember which ring has it. + */ + if (pool_pipr < pipr_min) { + pipr_min = pool_pipr; + ring_min = TM_QW2_HV_POOL; + } + } + } + + regs[TM_PIPR] = pipr_min; + /* CPPR has changed, check if we need to raise a pending exception */ - xive_tctx_notify(tctx, ring); + xive_tctx_notify(tctx, ring_min); } void xive_tctx_ipb_update(XiveTCTX *tctx, uint8_t ring, uint8_t ipb)