| Message ID | 20240716162617.32161-15-npiggin@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | ppc/pnv: Better big-core model, lpar-per-core, PC unit | expand |
On 7/16/24 18:26, Nicholas Piggin wrote: > POWER10 has a quirk in its ChipTOD addressing that requires the even > small-core to be selected even when programming the odd small-core. > This allows skiboot chiptod init to run in big-core mode. > > Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Thanks, C. > --- > include/hw/ppc/pnv.h | 1 + > include/hw/ppc/pnv_core.h | 7 +++++++ > hw/ppc/pnv.c | 7 ++++++- > hw/ppc/pnv_core.c | 2 ++ > target/ppc/timebase_helper.c | 9 +++++++++ > 5 files changed, 25 insertions(+), 1 deletion(-) > > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index 283ddd50e7..c56d152889 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -77,6 +77,7 @@ struct PnvMachineClass { > const char *compat; > int compat_size; > int max_smt_threads; > + bool quirk_tb_big_core; > > void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); > void (*i2c_init)(PnvMachineState *pnv); > diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h > index 50164e9e1f..c8784777a4 100644 > --- a/include/hw/ppc/pnv_core.h > +++ b/include/hw/ppc/pnv_core.h > @@ -27,6 +27,13 @@ > > /* Per-core ChipTOD / TimeBase state */ > typedef struct PnvCoreTODState { > + /* > + * POWER10 DD2.0 - big core TFMR drives the state machine on the even > + * small core. Skiboot has a workaround that targets the even small core > + * for CHIPTOD_TO_TB ops. > + */ > + bool big_core_quirk; > + > int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */ > int tod_sent_to_tb; /* chiptod sent TOD to the core TB */ > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 1d08176b75..322ab9073b 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -2290,11 +2290,12 @@ static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip, > > static void pnv_chip_core_realize(PnvChip *chip, Error **errp) > { > + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); > + PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(pnv); > Error *error = NULL; > PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); > const char *typename = pnv_chip_core_typename(chip); > int i, core_hwid; > - PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); > > if (!object_class_by_name(typename)) { > error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); > @@ -2335,8 +2336,11 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp) > &error_fatal); > object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core, > &error_fatal); > + object_property_set_bool(OBJECT(pnv_core), "quirk-tb-big-core", > + pmc->quirk_tb_big_core, &error_fatal); > object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), > &error_abort); > + > qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); > > /* Each core has an XSCOM MMIO region */ > @@ -2650,6 +2654,7 @@ static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) > pmc->compat = compat; > pmc->compat_size = sizeof(compat); > pmc->max_smt_threads = 4; > + pmc->quirk_tb_big_core = true; > pmc->dt_power_mgt = pnv_dt_power_mgt; > > xfc->match_nvt = pnv10_xive_match_nvt; > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index 43cfeaa2d4..1783795b23 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -364,6 +364,8 @@ static Property pnv_core_properties[] = { > DEFINE_PROP_UINT32("hwid", PnvCore, hwid, 0), > DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0), > DEFINE_PROP_BOOL("big-core", PnvCore, big_core, false), > + DEFINE_PROP_BOOL("quirk-tb-big-core", PnvCore, tod_state.big_core_quirk, > + false), > DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *), > DEFINE_PROP_END_OF_LIST(), > }; > diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c > index 44cacf065e..019b8ee41f 100644 > --- a/target/ppc/timebase_helper.c > +++ b/target/ppc/timebase_helper.c > @@ -20,6 +20,7 @@ > #include "cpu.h" > #include "hw/ppc/ppc.h" > #include "hw/ppc/pnv_core.h" > +#include "hw/ppc/pnv_chip.h" > #include "exec/helper-proto.h" > #include "exec/exec-all.h" > #include "qemu/log.h" > @@ -297,6 +298,14 @@ static PnvCoreTODState *cpu_get_tbst(PowerPCCPU *cpu) > { > PnvCore *pc = pnv_cpu_state(cpu)->pnv_core; > > + if (pc->big_core && pc->tod_state.big_core_quirk) { > + /* Must operate on the even small core */ > + int core_id = CPU_CORE(pc)->core_id; > + if (core_id & 1) { > + pc = pc->chip->cores[core_id & ~1]; > + } > + } > + > return &pc->tod_state; > } >
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 283ddd50e7..c56d152889 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -77,6 +77,7 @@ struct PnvMachineClass { const char *compat; int compat_size; int max_smt_threads; + bool quirk_tb_big_core; void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); void (*i2c_init)(PnvMachineState *pnv); diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h index 50164e9e1f..c8784777a4 100644 --- a/include/hw/ppc/pnv_core.h +++ b/include/hw/ppc/pnv_core.h @@ -27,6 +27,13 @@ /* Per-core ChipTOD / TimeBase state */ typedef struct PnvCoreTODState { + /* + * POWER10 DD2.0 - big core TFMR drives the state machine on the even + * small core. Skiboot has a workaround that targets the even small core + * for CHIPTOD_TO_TB ops. + */ + bool big_core_quirk; + int tb_ready_for_tod; /* core TB ready to receive TOD from chiptod */ int tod_sent_to_tb; /* chiptod sent TOD to the core TB */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 1d08176b75..322ab9073b 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2290,11 +2290,12 @@ static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip, static void pnv_chip_core_realize(PnvChip *chip, Error **errp) { + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); + PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(pnv); Error *error = NULL; PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); const char *typename = pnv_chip_core_typename(chip); int i, core_hwid; - PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); if (!object_class_by_name(typename)) { error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); @@ -2335,8 +2336,11 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp) &error_fatal); object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core, &error_fatal); + object_property_set_bool(OBJECT(pnv_core), "quirk-tb-big-core", + pmc->quirk_tb_big_core, &error_fatal); object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), &error_abort); + qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); /* Each core has an XSCOM MMIO region */ @@ -2650,6 +2654,7 @@ static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) pmc->compat = compat; pmc->compat_size = sizeof(compat); pmc->max_smt_threads = 4; + pmc->quirk_tb_big_core = true; pmc->dt_power_mgt = pnv_dt_power_mgt; xfc->match_nvt = pnv10_xive_match_nvt; diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 43cfeaa2d4..1783795b23 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -364,6 +364,8 @@ static Property pnv_core_properties[] = { DEFINE_PROP_UINT32("hwid", PnvCore, hwid, 0), DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0), DEFINE_PROP_BOOL("big-core", PnvCore, big_core, false), + DEFINE_PROP_BOOL("quirk-tb-big-core", PnvCore, tod_state.big_core_quirk, + false), DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/ppc/timebase_helper.c b/target/ppc/timebase_helper.c index 44cacf065e..019b8ee41f 100644 --- a/target/ppc/timebase_helper.c +++ b/target/ppc/timebase_helper.c @@ -20,6 +20,7 @@ #include "cpu.h" #include "hw/ppc/ppc.h" #include "hw/ppc/pnv_core.h" +#include "hw/ppc/pnv_chip.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "qemu/log.h" @@ -297,6 +298,14 @@ static PnvCoreTODState *cpu_get_tbst(PowerPCCPU *cpu) { PnvCore *pc = pnv_cpu_state(cpu)->pnv_core; + if (pc->big_core && pc->tod_state.big_core_quirk) { + /* Must operate on the even small core */ + int core_id = CPU_CORE(pc)->core_id; + if (core_id & 1) { + pc = pc->chip->cores[core_id & ~1]; + } + } + return &pc->tod_state; }
POWER10 has a quirk in its ChipTOD addressing that requires the even small-core to be selected even when programming the odd small-core. This allows skiboot chiptod init to run in big-core mode. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- include/hw/ppc/pnv.h | 1 + include/hw/ppc/pnv_core.h | 7 +++++++ hw/ppc/pnv.c | 7 ++++++- hw/ppc/pnv_core.c | 2 ++ target/ppc/timebase_helper.c | 9 +++++++++ 5 files changed, 25 insertions(+), 1 deletion(-)