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[174.21.76.141]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1fac15993c5sm90403755ad.244.2024.07.02.16.41.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jul 2024 16:41:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, iii@linux.ibm.com, david@redhat.com, balaton@eik.bme.hu Subject: [PATCH 2/2] target/arm: Use memset_ra, memmove_ra in helper-a64.c Date: Tue, 2 Jul 2024 16:41:55 -0700 Message-Id: <20240702234155.2106399-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240702234155.2106399-1-richard.henderson@linaro.org> References: <20240702234155.2106399-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Without this, qemu user will not unwind from the SIGSEGV properly and die with qemu-aarch64: QEMU internal SIGSEGV {code=ACCERR, addr=0x7d1b36ec2000} Segmentation fault Fill in the test case for ppc and s390x, which also use memset from within a helper (but don't currently crash fwiw). Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tcg/helper-a64.c | 10 ++-- tests/tcg/multiarch/memset-fault.c | 77 ++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+), 5 deletions(-) create mode 100644 tests/tcg/multiarch/memset-fault.c diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 0ea8668ab4..666bdb7c1a 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -971,7 +971,7 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in) } #endif - memset(mem, 0, blocklen); + memset_ra(mem, 0, blocklen, GETPC()); } void HELPER(unaligned_access)(CPUARMState *env, uint64_t addr, @@ -1120,7 +1120,7 @@ static uint64_t set_step(CPUARMState *env, uint64_t toaddr, } #endif /* Easy case: just memset the host memory */ - memset(mem, data, setsize); + memset_ra(mem, data, setsize, ra); return setsize; } @@ -1163,7 +1163,7 @@ static uint64_t set_step_tags(CPUARMState *env, uint64_t toaddr, } #endif /* Easy case: just memset the host memory */ - memset(mem, data, setsize); + memset_ra(mem, data, setsize, ra); mte_mops_set_tags(env, toaddr, setsize, *mtedesc); return setsize; } @@ -1497,7 +1497,7 @@ static uint64_t copy_step(CPUARMState *env, uint64_t toaddr, uint64_t fromaddr, } #endif /* Easy case: just memmove the host memory */ - memmove(wmem, rmem, copysize); + memmove_ra(wmem, rmem, copysize, ra); return copysize; } @@ -1572,7 +1572,7 @@ static uint64_t copy_step_rev(CPUARMState *env, uint64_t toaddr, * Easy case: just memmove the host memory. Note that wmem and * rmem here point to the *last* byte to copy. */ - memmove(wmem - (copysize - 1), rmem - (copysize - 1), copysize); + memmove_ra(wmem - (copysize - 1), rmem - (copysize - 1), copysize, ra); return copysize; } diff --git a/tests/tcg/multiarch/memset-fault.c b/tests/tcg/multiarch/memset-fault.c new file mode 100644 index 0000000000..0e8258a88f --- /dev/null +++ b/tests/tcg/multiarch/memset-fault.c @@ -0,0 +1,77 @@ +#include +#include +#include +#include +#include + +#if defined(__powerpc64__) +/* Needed for PT_* constants */ +#include +#endif + +static void *ptr; +static void *pc; + +static void test(void) +{ +#ifdef __aarch64__ + void *t; + asm("adr %0,1f; str %0,%1; 1: dc zva,%2" + : "=&r"(t), "=m"(pc) : "r"(ptr)); +#elif defined(__powerpc64__) + void *t; + asm("bl 0f; 0: mflr %0; addi %0,%0,1f-0b; std %0,%1; 1: dcbz 0,%2" + : "=&r"(t), "=m"(pc) : "r"(ptr) : "lr"); +#elif defined(__s390x__) + void *t; + asm("larl %0,1f; stg %0,%1; 1: xc 0(256,%2),0(%2)" + : "=&r"(t), "=m"(pc) : "r"(ptr)); +#else + *(int *)ptr = 0; +#endif +} + +static void *host_signal_pc(ucontext_t *uc) +{ +#ifdef __aarch64__ + return (void *)uc->uc_mcontext.pc; +#elif defined(__powerpc64__) + return (void *)uc->uc_mcontext.gp_regs[PT_NIP]; +#elif defined(__s390x__) + return (void *)uc->uc_mcontext.psw.addr; +#else + return NULL; +#endif +} + +static void sigsegv(int sig, siginfo_t *info, void *uc) +{ + assert(info->si_addr == ptr); + assert(host_signal_pc(uc) == pc); + exit(0); +} + +int main(void) +{ + static const struct sigaction sa = { + .sa_flags = SA_SIGINFO, + .sa_sigaction = sigsegv + }; + size_t size; + int r; + + size = getpagesize(); + ptr = mmap(NULL, size, PROT_READ | PROT_WRITE, + MAP_ANON | MAP_PRIVATE, -1, 0); + assert(ptr != MAP_FAILED); + + test(); + + r = sigaction(SIGSEGV, &sa, NULL); + assert(r == 0); + r = mprotect(ptr, size, PROT_NONE); + assert(r == 0); + + test(); + abort(); +}