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Thu, 21 Mar 2024 10:04:41 GMT Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CF4D25806F; Thu, 21 Mar 2024 10:04:36 +0000 (GMT) Received: from smtpav04.dal12v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5DACB58067; Thu, 21 Mar 2024 10:04:36 +0000 (GMT) Received: from gfwr516.rchland.ibm.com (unknown [9.10.239.105]) by smtpav04.dal12v.mail.ibm.com (Postfix) with ESMTP; Thu, 21 Mar 2024 10:04:36 +0000 (GMT) From: Saif Abrar To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: clg@kaod.org, npiggin@gmail.com, fbarrat@linux.ibm.com, mst@redhat.com, marcel.apfelbaum@gmail.com, cohuck@redhat.com, pbonzini@redhat.com, thuth@redhat.com, lvivier@redhat.com, saif.abrar@linux.vnet.ibm.com Subject: [PATCH 06/10] pnv/phb4: Set link-active status in HPSTAT and LMR registers Date: Thu, 21 Mar 2024 05:04:18 -0500 Message-Id: <20240321100422.5347-7-saif.abrar@linux.vnet.ibm.com> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> References: <20240321100422.5347-1-saif.abrar@linux.vnet.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: anYM_SM5mCyoCkn9hi5L2V8cdpVytosh X-Proofpoint-ORIG-GUID: 6Lu9-zAwNhJck7uhguMn11vN7xpz5KUP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxlogscore=999 bulkscore=0 adultscore=0 mlxscore=0 suspectscore=0 impostorscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2403140000 definitions=main-2403210069 Received-SPF: none client-ip=148.163.158.5; envelope-from=saif.abrar@linux.vnet.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Config-read the link-status register in the PCI-E macro, Depending on the link-active bit, set the link-active status in the HOTPLUG_STATUS and LINK_MANAGEMENT registers Also, clear the Presence-status active low bit in HOTPLUG_STATUS reg after config-reading the slot-status in the PCI-E macro. Signed-off-by: Saif Abrar --- hw/pci-host/pnv_phb4.c | 57 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 4e3a6b37f9..7b3d75bae6 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -516,6 +516,19 @@ static uint32_t get_exp_offset(PnvPHB4 *phb) return rpc->exp_offset; } +/* + * Config-read the link-status register in the PCI-E macro, + * convert to LE and check the link-active bit. + */ +static uint32_t is_link_active(PnvPHB4 *phb) +{ + uint32_t exp_offset = get_exp_offset(phb); + + return (bswap32(pnv_phb4_rc_config_read(phb, + exp_offset + PCI_EXP_LNKSTA, 4)) + & PCI_EXP_LNKSTA_DLLLA); +} + #define RC_CONFIG_WRITE(a, v) pnv_phb4_rc_config_write(phb, a, 4, v) /* @@ -757,6 +770,11 @@ static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, val = 0; break; + case PHB_PCIE_HOTPLUG_STATUS: + /* For normal operations, Simspeed diagnostic bit is always zero */ + val &= PHB_PCIE_HPSTAT_SIMDIAG; + break; + /* Read only registers */ case PHB_CPU_LOADSTORE_STATUS: case PHB_ETU_ERR_SUMMARY: @@ -968,8 +986,40 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) val |= PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; return val; + /* + * Read PCI-E registers and set status for: + * - Card present (active low bit 10) + * - Link active (bit 12) + */ case PHB_PCIE_HOTPLUG_STATUS: - /* Clear write-only bit */ + /* + * Presence-status bit hpi_present_n is active-low, with reset value 1. + * Start by setting this bit to 1, indicating the card is not present. + * Then check the PCI-E register and clear the bit if card is present. + */ + val |= PHB_PCIE_HPSTAT_PRESENCE; + + /* Get the PCI-E capability offset from the root-port */ + uint32_t exp_base = get_exp_offset(phb); + + /* + * Config-read the PCI-E macro register for slot-status. + * Method for config-read converts to BE value. + * To check actual bit in the PCI-E register, + * convert the value back to LE using bswap32(). + * Clear the Presence-status active low bit. + */ + if (bswap32(pnv_phb4_rc_config_read(phb, exp_base + PCI_EXP_SLTSTA, 4)) + & PCI_EXP_SLTSTA_PDS) { + val &= ~PHB_PCIE_HPSTAT_PRESENCE; + } + + /* Check if link is active and set the bit */ + if (is_link_active(phb)) { + val |= PHB_PCIE_HPSTAT_LINKACTIVE; + } + + /* Clear write-only resample-bit */ val &= ~PHB_PCIE_HPSTAT_RESAMPLE; return val; @@ -977,6 +1027,11 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) case PHB_PCIE_LMR: /* These write-only bits always read as 0 */ val &= ~(PHB_PCIE_LMR_CHANGELW | PHB_PCIE_LMR_RETRAINLINK); + + /* Check if link is active and set the bit */ + if (is_link_active(phb)) { + val |= PHB_PCIE_LMR_LINKACTIVE; + } return val; /* Silent simple reads */