@@ -96,5 +96,6 @@ struct nested_ppc_state {
};
void spapr_exit_nested(PowerPCCPU *cpu, int excp);
-
+bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry);
#endif /* HW_SPAPR_NESTED_H */
@@ -1362,7 +1362,6 @@ void spapr_init_all_lpcrs(target_ulong value, target_ulong mask)
}
}
-
static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
target_ulong lpid, ppc_v3_pate_t *entry)
{
@@ -1375,33 +1374,10 @@ static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
/* Copy PATE1:GR into PATE0:HR */
entry->dw0 = spapr->patb_entry & PATE0_HR;
entry->dw1 = spapr->patb_entry;
-
+ return true;
} else {
- uint64_t patb, pats;
-
- assert(lpid != 0);
-
- patb = spapr->nested_ptcr & PTCR_PATB;
- pats = spapr->nested_ptcr & PTCR_PATS;
-
- /* Check if partition table is properly aligned */
- if (patb & MAKE_64BIT_MASK(0, pats + 12)) {
- return false;
- }
-
- /* Calculate number of entries */
- pats = 1ull << (pats + 12 - 4);
- if (pats <= lpid) {
- return false;
- }
-
- /* Grab entry */
- patb += 16 * lpid;
- entry->dw0 = ldq_phys(CPU(cpu)->as, patb);
- entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8);
+ return spapr_get_pate_nested_hv(spapr, cpu, lpid, entry);
}
-
- return true;
}
#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
@@ -6,8 +6,38 @@
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "hw/ppc/spapr_nested.h"
+#include "mmu-book3s-v3.h"
#ifdef CONFIG_TCG
+
+bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry)
+{
+ uint64_t patb, pats;
+
+ assert(lpid != 0);
+
+ patb = spapr->nested_ptcr & PTCR_PATB;
+ pats = spapr->nested_ptcr & PTCR_PATS;
+
+ /* Check if partition table is properly aligned */
+ if (patb & MAKE_64BIT_MASK(0, pats + 12)) {
+ return false;
+ }
+
+ /* Calculate number of entries */
+ pats = 1ull << (pats + 12 - 4);
+ if (pats <= lpid) {
+ return false;
+ }
+
+ /* Grab entry */
+ patb += 16 * lpid;
+ entry->dw0 = ldq_phys(CPU(cpu)->as, patb);
+ entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8);
+ return true;
+}
+
#define PRTS_MASK 0x1f
static target_ulong h_set_ptbl(PowerPCCPU *cpu,
@@ -405,4 +435,10 @@ void spapr_unregister_nested_hv(void)
{
/* DO NOTHING */
}
+
+bool spapr_get_pate_nested_hv(SpaprMachineState *spapr, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry)
+{
+ return false;
+}
#endif