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[PULL,18/30] target/ppc: Add ISA v3.1 LEV indication in SRR1 for system call interrupts

Message ID 20230626055647.1147743-19-clg@kaod.org
State Handled Elsewhere
Headers show
Series [PULL,01/30] target/ppc: gdbstub init spr gdb_id for all CPUs | expand

Commit Message

Cédric Le Goater June 26, 2023, 5:56 a.m. UTC 
From: Nicholas Piggin <npiggin@gmail.com>

System call interrupts in ISA v3.1 CPUs add a LEV indication in SRR1
that corresponds with the LEV field of the instruction that caused the
interrupt.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 target/ppc/excp_helper.c | 4 ++++
 1 file changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 2a0070cf4378..8e2fec3551b9 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1591,6 +1591,10 @@  static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
             vhc->hypercall(cpu->vhyp, cpu);
             return;
         }
+        if (env->insns_flags2 & PPC2_ISA310) {
+            /* ISAv3.1 puts LEV into SRR1 */
+            msr |= lev << 20;
+        }
         if (lev == 1) {
             new_msr |= (target_ulong)MSR_HVB;
         }