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Tue, 30 May 2023 16:11:31 GMT Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 89E032004D; Tue, 30 May 2023 16:11:31 +0000 (GMT) Received: from smtpav07.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 456A420043; Tue, 30 May 2023 16:11:31 +0000 (GMT) Received: from borneo.ibmuc.com (unknown [9.171.3.249]) by smtpav07.fra02v.mail.ibm.com (Postfix) with ESMTP; Tue, 30 May 2023 16:11:31 +0000 (GMT) From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/4] pnv/xive2: Handle TIMA access through all ports Date: Tue, 30 May 2023 18:11:29 +0200 Message-Id: <20230530161129.313258-5-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230530161129.313258-1-fbarrat@linux.ibm.com> References: <20230530161129.313258-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: T1HWBFeMG1yrgYuXsUF0pGQ2lNSQCdC8 X-Proofpoint-ORIG-GUID: rLwe3mfY8mSeJS9hSxCV1Pplyf69CR7F X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-30_12,2023-05-30_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=939 priorityscore=1501 adultscore=0 impostorscore=0 suspectscore=0 clxscore=1015 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305300127 Received-SPF: pass client-ip=148.163.158.5; envelope-from=fbarrat@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org The Thread Interrupt Management Area (TIMA) can be accessed through 4 ports/snoop buses, targeted by the address. The base address of a TIMA is using port 0 and the other ports are 0x80 apart. Using one port or another can be useful to balance the load on the snoop buses. The TIMA registers are in the 0x0 -> 0x3F range and there are 2 indication bits for special operations (bits 10 and 11; everything fits on a 4k page). So the port address bits fall in between and are "don't care" for the hardware when processing the TIMA operation. So this patch filters out those port address bits so that a TIMA operation can be triggered using any port. It is also true for indirect access (through the IC BAR) and it's actually nothing new, it was already the case on P9. Which helps here, as the TIMA handling code is common between P9 (xive) and P10 (xive2). Signed-off-by: Frederic Barrat Reviewed-by: Cédric Le Goater --- hw/intc/pnv_xive2.c | 4 ++++ hw/intc/xive.c | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index 132f82a035..c80316657a 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -1662,6 +1662,8 @@ static void pnv_xive2_tm_write(void *opaque, hwaddr offset, bool gen1_tima_os = xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; + offset &= 0xC3F; /* See comment in xive_tctx_tm_write() */ + /* TODO: should we switch the TM ops table instead ? */ if (!gen1_tima_os && offset == HV_PUSH_OS_CTX_OFFSET) { xive2_tm_push_os_ctx(xptr, tctx, offset, value, size); @@ -1681,6 +1683,8 @@ static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size) bool gen1_tima_os = xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS; + offset &= 0xC3F; /* See comment in xive_tctx_tm_read() */ + /* TODO: should we switch the TM ops table instead ? */ if (!gen1_tima_os && offset == HV_PULL_OS_CTX_OFFSET) { return xive2_tm_pull_os_ctx(xptr, tctx, offset, size); diff --git a/hw/intc/xive.c b/hw/intc/xive.c index a986b96843..c1abfae31d 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -527,6 +527,15 @@ void xive_tctx_tm_write(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, trace_xive_tctx_tm_write(offset, size, value); + /* + * The TIMA can be accessed through 4 ports/snoop buses, with + * addresses 0x80 apart. + * However, the offset bits between the "special op" bits and the + * MSB of the range used for the TIMA registers are "don't care" + * for the hardware, so we filter them out. + */ + offset &= 0xC3F; + /* * TODO: check V bit in Q[0-3]W2 */ @@ -566,6 +575,15 @@ uint64_t xive_tctx_tm_read(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset, const XiveTmOp *xto; uint64_t ret; + /* + * The TIMA can be accessed through 4 ports/snoop buses, with + * addresses 0x80 apart. + * However, the offset bits between the "special op" bits and the + * MSB of the range used for the TIMA registers are "don't care" + * for the hardware, so we filter them out. + */ + offset &= 0xC3F; + /* * TODO: check V bit in Q[0-3]W2 */