@@ -1679,6 +1679,118 @@ void ppc_cpu_do_interrupt(CPUState *cs)
}
#if defined(TARGET_PPC64)
+static int p7_next_unmasked_interrupt(CPUPPCState *env)
+{
+ bool async_deliver;
+
+ /* External reset */
+ if (env->pending_interrupts & PPC_INTERRUPT_RESET) {
+ return PPC_INTERRUPT_RESET;
+ }
+ /* Machine check exception */
+ if (env->pending_interrupts & PPC_INTERRUPT_MCK) {
+ return PPC_INTERRUPT_MCK;
+ }
+#if 0 /* TODO */
+ /* External debug exception */
+ if (env->pending_interrupts & PPC_INTERRUPT_DEBUG) {
+ return PPC_INTERRUPT_DEBUG;
+ }
+#endif
+
+ /*
+ * For interrupts that gate on MSR:EE, we need to do something a
+ * bit more subtle, as we need to let them through even when EE is
+ * clear when coming out of some power management states (in order
+ * for them to become a 0x100).
+ */
+ async_deliver = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;
+
+ /* Hypervisor decrementer exception */
+ if (env->pending_interrupts & PPC_INTERRUPT_HDECR) {
+ /* LPCR will be clear when not supported so this will work */
+ bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
+ if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) {
+ /* HDEC clears on delivery */
+ return PPC_INTERRUPT_HDECR;
+ }
+ }
+
+ /* Hypervisor virtualization interrupt */
+ if (env->pending_interrupts & PPC_INTERRUPT_HVIRT) {
+ /* LPCR will be clear when not supported so this will work */
+ bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE);
+ if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) {
+ return PPC_INTERRUPT_HVIRT;
+ }
+ }
+
+ /* External interrupt can ignore MSR:EE under some circumstances */
+ if (env->pending_interrupts & PPC_INTERRUPT_EXT) {
+ bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
+ bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
+ /* HEIC blocks delivery to the hypervisor */
+ if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) &&
+ !FIELD_EX64(env->msr, MSR, PR))) ||
+ (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) {
+ return PPC_INTERRUPT_EXT;
+ }
+ }
+ if (FIELD_EX64(env->msr, MSR, CE)) {
+ /* External critical interrupt */
+ if (env->pending_interrupts & PPC_INTERRUPT_CEXT) {
+ return PPC_INTERRUPT_CEXT;
+ }
+ }
+ if (async_deliver != 0) {
+ /* Watchdog timer on embedded PowerPC */
+ if (env->pending_interrupts & PPC_INTERRUPT_WDT) {
+ return PPC_INTERRUPT_WDT;
+ }
+ if (env->pending_interrupts & PPC_INTERRUPT_CDOORBELL) {
+ return PPC_INTERRUPT_CDOORBELL;
+ }
+ /* Fixed interval timer on embedded PowerPC */
+ if (env->pending_interrupts & PPC_INTERRUPT_FIT) {
+ return PPC_INTERRUPT_FIT;
+ }
+ /* Programmable interval timer on embedded PowerPC */
+ if (env->pending_interrupts & PPC_INTERRUPT_PIT) {
+ return PPC_INTERRUPT_PIT;
+ }
+ /* Decrementer exception */
+ if (env->pending_interrupts & PPC_INTERRUPT_DECR) {
+ return PPC_INTERRUPT_DECR;
+ }
+ if (env->pending_interrupts & PPC_INTERRUPT_DOORBELL) {
+ return PPC_INTERRUPT_DOORBELL;
+ }
+ if (env->pending_interrupts & PPC_INTERRUPT_HDOORBELL) {
+ return PPC_INTERRUPT_HDOORBELL;
+ }
+ if (env->pending_interrupts & PPC_INTERRUPT_PERFM) {
+ return PPC_INTERRUPT_PERFM;
+ }
+ /* Thermal interrupt */
+ if (env->pending_interrupts & PPC_INTERRUPT_THERM) {
+ return PPC_INTERRUPT_THERM;
+ }
+ /* EBB exception */
+ if (env->pending_interrupts & PPC_INTERRUPT_EBB) {
+ /*
+ * EBB exception must be taken in problem state and
+ * with BESCR_GE set.
+ */
+ if (FIELD_EX64(env->msr, MSR, PR) &&
+ (env->spr[SPR_BESCR] & BESCR_GE)) {
+ return PPC_INTERRUPT_EBB;
+ }
+ }
+ }
+
+ return 0;
+}
+
#define P8_UNUSED_INTERRUPTS \
(PPC_INTERRUPT_RESET | PPC_INTERRUPT_DEBUG | PPC_INTERRUPT_HVIRT | \
PPC_INTERRUPT_CEXT | PPC_INTERRUPT_WDT | PPC_INTERRUPT_CDOORBELL | \
@@ -1961,6 +2073,8 @@ static int ppc_next_unmasked_interrupt(CPUPPCState *env)
{
switch (env->excp_model) {
#if defined(TARGET_PPC64)
+ case POWERPC_EXCP_POWER7:
+ return p7_next_unmasked_interrupt(env);
case POWERPC_EXCP_POWER8:
return p8_next_unmasked_interrupt(env);
case POWERPC_EXCP_POWER9:
The new method is identical to ppc_next_unmasked_interrupt_generic, processor-specific code will be added/removed in the following patches. No functional change intended. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> --- v2: - Renamed the method from ppc_pending_interrupt_p7 to p7_next_unmasked_interrupt; - Processor-specific stuff moved to the following patches to ease review. --- target/ppc/excp_helper.c | 114 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 114 insertions(+)