From patchwork Mon Aug 1 13:10:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 1662600 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4LxJw01Lp4z9sGV for ; Mon, 1 Aug 2022 23:32:48 +1000 (AEST) Received: from localhost ([::1]:48294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oIVXK-0003iT-0e for incoming@patchwork.ozlabs.org; Mon, 01 Aug 2022 09:32:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56704) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oIVDS-0005wP-HB; Mon, 01 Aug 2022 09:12:14 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:36449 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oIVDN-0007Ny-5T; Mon, 01 Aug 2022 09:12:14 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4LxJRy52KHz4xGL; Mon, 1 Aug 2022 23:11:58 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4LxJRt0H8Mz4xGX; Mon, 1 Aug 2022 23:11:53 +1000 (AEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-ppc@nongnu.org Cc: Daniel Henrique Barboza , qemu-devel@nongnu.org, BALATON Zoltan , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PATCH 17/19] ppc/ppc405: QOM'ify FPGA Date: Mon, 1 Aug 2022 15:10:37 +0200 Message-Id: <20220801131039.1693913-18-clg@kaod.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220801131039.1693913-1-clg@kaod.org> References: <20220801131039.1693913-1-clg@kaod.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=LBbo=YF=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-ppc" Signed-off-by: Cédric Le Goater Reviewed-by: Daniel Henrique Barboza --- hw/ppc/ppc405_boards.c | 55 +++++++++++++++++++++++++++++------------- 1 file changed, 38 insertions(+), 17 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 82b51cc457fa..2900c267b7ac 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -71,18 +71,23 @@ OBJECT_DECLARE_SIMPLE_TYPE(Ppc405MachineState, PPC405_MACHINE); * - NVRAM (0xF0000000) * - FPGA (0xF0300000) */ -typedef struct ref405ep_fpga_t ref405ep_fpga_t; -struct ref405ep_fpga_t { + +#define TYPE_PPC405_FPGA "ppc405-fpga" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405FpgaState, PPC405_FPGA); +struct Ppc405FpgaState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + uint8_t reg0; uint8_t reg1; }; static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size) { - ref405ep_fpga_t *fpga; + Ppc405FpgaState *fpga = PPC405_FPGA(opaque); uint32_t ret; - fpga = opaque; switch (addr) { case 0x0: ret = fpga->reg0; @@ -101,9 +106,8 @@ static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size) static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, unsigned size) { - ref405ep_fpga_t *fpga; + Ppc405FpgaState *fpga = PPC405_FPGA(opaque); - fpga = opaque; switch (addr) { case 0x0: /* Read only */ @@ -126,27 +130,39 @@ static const MemoryRegionOps ref405ep_fpga_ops = { .endianness = DEVICE_BIG_ENDIAN, }; -static void ref405ep_fpga_reset (void *opaque) +static void ref405ep_fpga_reset(DeviceState *dev) { - ref405ep_fpga_t *fpga; + Ppc405FpgaState *fpga = PPC405_FPGA(dev); - fpga = opaque; fpga->reg0 = 0x00; fpga->reg1 = 0x0F; } -static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base) +static void ref405ep_fpga_realize(DeviceState *dev, Error **errp) { - ref405ep_fpga_t *fpga; - MemoryRegion *fpga_memory = g_new(MemoryRegion, 1); + Ppc405FpgaState *s = PPC405_FPGA(dev); - fpga = g_new0(ref405ep_fpga_t, 1); - memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga, + memory_region_init_io(&s->iomem, OBJECT(s), &ref405ep_fpga_ops, s, "fpga", 0x00000100); - memory_region_add_subregion(sysmem, base, fpga_memory); - qemu_register_reset(&ref405ep_fpga_reset, fpga); + sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); +} + +static void ref405ep_fpga_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = ref405ep_fpga_realize; + dc->user_creatable = false; + dc->reset = ref405ep_fpga_reset; } +static const TypeInfo ref405ep_fpga_type = { + .name = TYPE_PPC405_FPGA, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(Ppc405FpgaState), + .class_init = ref405ep_fpga_class_init, +}; + /* * CPU reset handler when booting directly from a loaded kernel */ @@ -325,7 +341,11 @@ static void ref405ep_init(MachineState *machine) ppc405_init(machine); /* Register FPGA */ - ref405ep_fpga_init(get_system_memory(), PPC405EP_FPGA_BASE); + dev = qdev_new(TYPE_PPC405_FPGA); + object_property_add_child(OBJECT(machine), "fpga", OBJECT(dev)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PPC405EP_FPGA_BASE); + /* Register NVRAM */ dev = qdev_new("sysbus-m48t08"); qdev_prop_set_int32(dev, "base-year", 1968); @@ -370,6 +390,7 @@ static void ppc405_machine_init(void) { type_register_static(&ppc405_machine_type); type_register_static(&ref405ep_type); + type_register_static(&ref405ep_fpga_type); } type_init(ppc405_machine_init)