diff mbox series

[5/7] target/ppc: use int128.h methods in vsubuqm

Message ID 20220606150037.338931-6-matheus.ferst@eldorado.org.br
State Accepted, archived
Headers show
Series Remove CONFIG_INT128 conditional code from target/ppc/* | expand

Commit Message

Matheus K. Ferst June 6, 2022, 3 p.m. UTC 
And also move the insn to decodetree

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/helper.h                 |  2 +-
 target/ppc/insn32.decode            |  2 ++
 target/ppc/int_helper.c             | 19 ++-----------------
 target/ppc/translate/vmx-impl.c.inc |  5 ++---
 target/ppc/translate/vmx-ops.c.inc  |  2 +-
 5 files changed, 8 insertions(+), 22 deletions(-)

Comments

Víctor Colombo June 27, 2022, 4:26 p.m. UTC | #1 
On 06/06/2022 12:00, Matheus Ferst wrote:
> And also move the insn to decodetree
> 
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> ---
>   target/ppc/helper.h                 |  2 +-
>   target/ppc/insn32.decode            |  2 ++
>   target/ppc/int_helper.c             | 19 ++-----------------
>   target/ppc/translate/vmx-impl.c.inc |  5 ++---
>   target/ppc/translate/vmx-ops.c.inc  |  2 +-
>   5 files changed, 8 insertions(+), 22 deletions(-)
> 
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index f6b1b2fad2..1c02ad85e5 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -208,7 +208,7 @@ DEF_HELPER_FLAGS_3(VADDUQM, TCG_CALL_NO_RWG, void, avr, avr, avr)
>   DEF_HELPER_FLAGS_4(VADDECUQ, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
>   DEF_HELPER_FLAGS_4(VADDEUQM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
>   DEF_HELPER_FLAGS_3(VADDCUQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
> -DEF_HELPER_FLAGS_3(vsubuqm, TCG_CALL_NO_RWG, void, avr, avr, avr)
> +DEF_HELPER_FLAGS_3(VSUBUQM, TCG_CALL_NO_RWG, void, avr, avr, avr)
>   DEF_HELPER_FLAGS_4(vsubecuq, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
>   DEF_HELPER_FLAGS_4(vsubeuqm, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
>   DEF_HELPER_FLAGS_3(vsubcuq, TCG_CALL_NO_RWG, void, avr, avr, avr)
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 35252ddd4f..a8d3a5a8a1 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -556,6 +556,8 @@ VADDUQM         000100 ..... ..... ..... 00100000000    @VX
>   VADDEUQM        000100 ..... ..... ..... ..... 111100   @VA
>   VADDECUQ        000100 ..... ..... ..... ..... 111101   @VA
> 
> +VSUBUQM         000100 ..... ..... ..... 10100000000    @VX
> +
>   VEXTSB2W        000100 ..... 10000 ..... 11000000010    @VX_tb
>   VEXTSH2W        000100 ..... 10001 ..... 11000000010    @VX_tb
>   VEXTSB2D        000100 ..... 11000 ..... 11000000010    @VX_tb
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index a12f2831ac..625cc92a55 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -2176,12 +2176,6 @@ VGENERIC_DO(popcntd, u64)
> 
>   #undef VGENERIC_DO
> 
> -#if HOST_BIG_ENDIAN
> -#define QW_ONE { .u64 = { 0, 1 } }
> -#else
> -#define QW_ONE { .u64 = { 1, 0 } }
> -#endif
> -
>   #ifndef CONFIG_INT128
> 
>   static inline void avr_qw_not(ppc_avr_t *t, ppc_avr_t a)
> @@ -2245,18 +2239,9 @@ void helper_VADDECUQ(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
>       r->VsrD(1) = carry_out;
>   }
> 
> -void helper_vsubuqm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> +void helper_VSUBUQM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
>   {
> -#ifdef CONFIG_INT128
> -    r->u128 = a->u128 - b->u128;
> -#else
> -    ppc_avr_t tmp;
> -    ppc_avr_t one = QW_ONE;
> -
> -    avr_qw_not(&tmp, *b);
> -    avr_qw_add(&tmp, *a, tmp);
> -    avr_qw_add(r, tmp, one);
> -#endif
> +    r->s128 = int128_sub(a->s128, b->s128);
>   }
> 
>   void helper_vsubeuqm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
> diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
> index 8c0e5bcc03..1e665534c3 100644
> --- a/target/ppc/translate/vmx-impl.c.inc
> +++ b/target/ppc/translate/vmx-impl.c.inc
> @@ -1234,7 +1234,6 @@ GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
>   GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
>   GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
>   GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
> -GEN_VXFORM(vsubuqm, 0, 20);
>   GEN_VXFORM(vsubcuq, 0, 21);
>   GEN_VXFORM3(vsubeuqm, 31, 0);
>   GEN_VXFORM3(vsubecuq, 31, 0);
> @@ -2858,8 +2857,6 @@ GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
>                   bcdus, PPC_NONE, PPC2_ISA300)
>   GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
>                   bcdtrunc, PPC_NONE, PPC2_ISA300)
> -GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
> -                bcdtrunc, PPC_NONE, PPC2_ISA300)
>   GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
>                   bcdutrunc, PPC_NONE, PPC2_ISA300)
> 
> @@ -3102,6 +3099,8 @@ TRANS_FLAGS2(ALTIVEC_207, VADDUQM, do_vx_helper, gen_helper_VADDUQM)
> 
>   TRANS_FLAGS2(ALTIVEC_207, VPMSUMD, do_vx_helper, gen_helper_VPMSUMD)
> 
> +TRANS_FLAGS2(ALTIVEC_207, VSUBUQM, do_vx_helper, gen_helper_VSUBUQM)
> +
>   static bool do_vx_vmuleo(DisasContext *ctx, arg_VX *a, bool even,
>                            void (*gen_mul)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
>   {
> diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
> index 33e05929cb..9feef9afee 100644
> --- a/target/ppc/translate/vmx-ops.c.inc
> +++ b/target/ppc/translate/vmx-ops.c.inc
> @@ -126,7 +126,7 @@ GEN_VXFORM(vsubuws, 0, 26),
>   GEN_VXFORM_DUAL(vsubsbs, bcdtrunc, 0, 28, PPC_ALTIVEC, PPC2_ISA300),
>   GEN_VXFORM(vsubshs, 0, 29),
>   GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
> -GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
> +GEN_VXFORM_300(bcdtrunc, 0, 20),
>   GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300),
>   GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
>   GEN_VXFORM(vsl, 2, 7),
> --
> 2.25.1
> 
> 

Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
diff mbox series

Patch

diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index f6b1b2fad2..1c02ad85e5 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -208,7 +208,7 @@  DEF_HELPER_FLAGS_3(VADDUQM, TCG_CALL_NO_RWG, void, avr, avr, avr)
 DEF_HELPER_FLAGS_4(VADDECUQ, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
 DEF_HELPER_FLAGS_4(VADDEUQM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
 DEF_HELPER_FLAGS_3(VADDCUQ, TCG_CALL_NO_RWG, void, avr, avr, avr)
-DEF_HELPER_FLAGS_3(vsubuqm, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VSUBUQM, TCG_CALL_NO_RWG, void, avr, avr, avr)
 DEF_HELPER_FLAGS_4(vsubecuq, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
 DEF_HELPER_FLAGS_4(vsubeuqm, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
 DEF_HELPER_FLAGS_3(vsubcuq, TCG_CALL_NO_RWG, void, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 35252ddd4f..a8d3a5a8a1 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -556,6 +556,8 @@  VADDUQM         000100 ..... ..... ..... 00100000000    @VX
 VADDEUQM        000100 ..... ..... ..... ..... 111100   @VA
 VADDECUQ        000100 ..... ..... ..... ..... 111101   @VA
 
+VSUBUQM         000100 ..... ..... ..... 10100000000    @VX
+
 VEXTSB2W        000100 ..... 10000 ..... 11000000010    @VX_tb
 VEXTSH2W        000100 ..... 10001 ..... 11000000010    @VX_tb
 VEXTSB2D        000100 ..... 11000 ..... 11000000010    @VX_tb
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index a12f2831ac..625cc92a55 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -2176,12 +2176,6 @@  VGENERIC_DO(popcntd, u64)
 
 #undef VGENERIC_DO
 
-#if HOST_BIG_ENDIAN
-#define QW_ONE { .u64 = { 0, 1 } }
-#else
-#define QW_ONE { .u64 = { 1, 0 } }
-#endif
-
 #ifndef CONFIG_INT128
 
 static inline void avr_qw_not(ppc_avr_t *t, ppc_avr_t a)
@@ -2245,18 +2239,9 @@  void helper_VADDECUQ(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
     r->VsrD(1) = carry_out;
 }
 
-void helper_vsubuqm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+void helper_VSUBUQM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
 {
-#ifdef CONFIG_INT128
-    r->u128 = a->u128 - b->u128;
-#else
-    ppc_avr_t tmp;
-    ppc_avr_t one = QW_ONE;
-
-    avr_qw_not(&tmp, *b);
-    avr_qw_add(&tmp, *a, tmp);
-    avr_qw_add(r, tmp, one);
-#endif
+    r->s128 = int128_sub(a->s128, b->s128);
 }
 
 void helper_vsubeuqm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 8c0e5bcc03..1e665534c3 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1234,7 +1234,6 @@  GEN_VXFORM_SAT(vsubuws, MO_32, sub, ussub, 0, 26);
 GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28);
 GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29);
 GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30);
-GEN_VXFORM(vsubuqm, 0, 20);
 GEN_VXFORM(vsubcuq, 0, 21);
 GEN_VXFORM3(vsubeuqm, 31, 0);
 GEN_VXFORM3(vsubecuq, 31, 0);
@@ -2858,8 +2857,6 @@  GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
                 bcdus, PPC_NONE, PPC2_ISA300)
 GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
                 bcdtrunc, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
-                bcdtrunc, PPC_NONE, PPC2_ISA300)
 GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
                 bcdutrunc, PPC_NONE, PPC2_ISA300)
 
@@ -3102,6 +3099,8 @@  TRANS_FLAGS2(ALTIVEC_207, VADDUQM, do_vx_helper, gen_helper_VADDUQM)
 
 TRANS_FLAGS2(ALTIVEC_207, VPMSUMD, do_vx_helper, gen_helper_VPMSUMD)
 
+TRANS_FLAGS2(ALTIVEC_207, VSUBUQM, do_vx_helper, gen_helper_VSUBUQM)
+
 static bool do_vx_vmuleo(DisasContext *ctx, arg_VX *a, bool even,
                          void (*gen_mul)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
 {
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index 33e05929cb..9feef9afee 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -126,7 +126,7 @@  GEN_VXFORM(vsubuws, 0, 26),
 GEN_VXFORM_DUAL(vsubsbs, bcdtrunc, 0, 28, PPC_ALTIVEC, PPC2_ISA300),
 GEN_VXFORM(vsubshs, 0, 29),
 GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
+GEN_VXFORM_300(bcdtrunc, 0, 20),
 GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300),
 GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
 GEN_VXFORM(vsl, 2, 7),