diff mbox series

[PULL,09/42] target/ppc: booke: Alignment interrupt cleanup

Message ID	20220210130008.2599950-10-clg@kaod.org
State	Handled Elsewhere
Headers	show Return-Path: <qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: =?utf-8?q?C=C3=A9dric_Le_Goater?= <clg@kaod.org> To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PULL 09/42] target/ppc: booke: Alignment interrupt cleanup Date: Thu, 10 Feb 2022 13:59:35 +0100 Message-Id: <20220210130008.2599950-10-clg@kaod.org> In-Reply-To: <20220210130008.2599950-1-clg@kaod.org> References: <20220210130008.2599950-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Received-SPF: softfail client-ip=148.163.158.5; envelope-from=clg@kaod.org; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Cc: Peter Maydell <peter.maydell@linaro.org>, Richard Henderson <richard.henderson@linaro.org>, =?utf-8?q?C=C3=A9dric_Le_?= =?utf-8?q?Goater?= <clg@kaod.org>, Fabiano Rosas <farosas@linux.ibm.com> Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-ppc" <qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/42] target/ppc: Remove 440x4 CPU \| expand [PULL,01/42] target/ppc: Remove 440x4 CPU [PULL,02/42] target/ppc: Introduce powerpc_excp_booke [PULL,03/42] target/ppc: Simplify powerpc_excp_booke [PULL,04/42] target/ppc: booke: Critical exception cleanup [PULL,05/42] target/ppc: booke: Machine Check cleanups [PULL,06/42] target/ppc: booke: Data Storage exception cleanup [PULL,07/42] target/ppc: booke: Instruction storage exception cleanup [PULL,08/42] target/ppc: booke: External interrupt cleanup [PULL,09/42] target/ppc: booke: Alignment interrupt cleanup [PULL,10/42] target/ppc: booke: System Call exception cleanup [PULL,11/42] target/ppc: booke: Watchdog Timer interrupt [PULL,12/42] target/ppc: booke: System Reset exception cleanup [PULL,13/42] target/ppc: Fix radix logging [PULL,14/42] target/ppc: Remove PowerPC 601 CPUs [PULL,15/42] target/ppc: Merge exception model IDs for 6xx CPUs [PULL,16/42] target/ppc: Introduce powerpc_excp_6xx [PULL,17/42] target/ppc: Simplify powerpc_excp_6xx [PULL,18/42] target/ppc: 6xx: Critical exception cleanup [PULL,19/42] target/ppc: 6xx: Machine Check exception cleanup [PULL,20/42] target/ppc: 6xx: External interrupt cleanup [PULL,21/42] target/ppc: 6xx: Program exception cleanup [PULL,22/42] target/ppc: 6xx: System Call exception cleanup [PULL,23/42] target/ppc: 6xx: System Reset interrupt cleanup [PULL,24/42] target/ppc: 6xx: Software TLB exceptions cleanup [PULL,25/42] target/ppc: 6xx: Set SRRs directly in exception code [PULL,26/42] target/ppc: Merge 7x5 and 7x0 exception model IDs [PULL,27/42] target/ppc: Introduce powerpc_excp_7xx [PULL,28/42] target/ppc: Simplify powerpc_excp_7xx [PULL,29/42] target/ppc: 7xx: Machine Check exception cleanup [PULL,30/42] target/ppc: 7xx: External interrupt cleanup [PULL,31/42] target/ppc: 7xx: Program exception cleanup [PULL,32/42] target/ppc: 7xx: System Call exception cleanup [PULL,33/42] target/ppc: 7xx: System Reset cleanup [PULL,34/42] target/ppc: 7xx: Software TLB cleanup [PULL,35/42] target/ppc: 7xx: Set SRRs directly in exception code [PULL,36/42] target/ppc: Remove powerpc_excp_legacy [PULL,37/42] target/ppc: powerpc_excp: Move common code to the caller function [PULL,38/42] target/ppc: Assert if MSR bits differ from msr_mask during exceptions [PULL,39/42] target/ppc: books: Remove excp_model argument from ppc_excp_apply_ail [PULL,40/42] target/ppc: Change VSX instructions behavior to fill with zeros [PULL,41/42] docs: rstfy confidential guest documentation [PULL,42/42] spapr/vof: Install rom and nvram binaries

Commit Message

Cédric Le Goater Feb. 10, 2022, 12:59 p.m. UTC

From: Fabiano Rosas <farosas@linux.ibm.com>

BookE has no DSISR or DAR. The proper registers ESR and DEAR were
already set at this point.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220128224018.1228062-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 target/ppc/excp_helper.c | 7 -------
 1 file changed, 7 deletions(-)

diff mbox series

Patch

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 6d86ae04eb8b..dfcb9995b8a2 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -844,13 +844,6 @@  static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
         }
         break;
     case POWERPC_EXCP_ALIGN:     /* Alignment exception                      */
-        /* Get rS/rD and rA from faulting opcode */
-        /*
-         * Note: the opcode fields will not be set properly for a
-         * direct store load/store, but nobody cares as nobody
-         * actually uses direct store segments.
-         */
-        env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
         break;
     case POWERPC_EXCP_PROGRAM:   /* Program exception                        */
         switch (env->error_code & ~0xF) {