| Message ID | 20211216140951.1183987-1-matheus.ferst@eldorado.org.br |
|---|---|
| State | Superseded |
| Headers | show |
| Series | tests/tcg/ppc64le: remove INT128 requirement to run non_signalling_xscv | expand |
On 12/16/21 6:09 AM, matheus.ferst@eldorado.org.br wrote: > + asm("mtvsrd 0, %3\n\t" \ > + "xxswapd 0, 0\n\t" \ > + "mtvsrd 0, %2\n\t" \ This doesn't work. The lower half of vs0 is undefined after mtvsrd. You actually want mtvsrdd 0, %2, %3, with "b" as the constraint for bh. > + "mfvsrd %0, 0\n\t" \ > + "xxswapd 0, 0\n\t" \ > + "mfvsrd %1, 0\n\t" \ Drop the xxswapd and use mfvsrld. Otherwise it looks ok. r~
On 17/12/2021 20:54, Richard Henderson wrote: > [E-MAIL EXTERNO] Não clique em links ou abra anexos, a menos que você > possa confirmar o remetente e saber que o conteúdo é seguro. Em caso de > e-mail suspeito entre imediatamente em contato com o DTI. > > On 12/16/21 6:09 AM, matheus.ferst@eldorado.org.br wrote: >> + asm("mtvsrd 0, >> %3\n\t" \ >> + "xxswapd 0, >> 0\n\t" \ >> + "mtvsrd 0, >> %2\n\t" \ > > This doesn't work. The lower half of vs0 is undefined after mtvsrd. > You actually want mtvsrdd 0, %2, %3, with "b" as the constraint for bh. > >> + "mfvsrd %0, >> 0\n\t" \ >> + "xxswapd 0, >> 0\n\t" \ >> + "mfvsrd %1, >> 0\n\t" \ > > Drop the xxswapd and use mfvsrld. > > Otherwise it looks ok. > > > r~ I'd like to avoid mtvsrdd/mfvsrld because they were introduced in PowerISA v3.0, and xscvspdpn/xscvdpspn are from v2.07. How about asm("mtvsrd 0, %2\n\t" "mtvsrd 1, %3\n\t" "xxmrghd 0, 0, 1\n\t" INSN " 0, 0\n\t" "mfvsrd %0, 0\n\t" "xxswapd 0, 0\n\t" "mfvsrd %1, 0\n\t" : "=r" (th), "=r" (tl) : "r" (bh), "r" (bl) : "vs0", "vs1"); ? Thanks, Matheus K. Ferst Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/> Analista de Software Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
On 12/20/21 4:18 AM, Matheus K. Ferst wrote: > I'd like to avoid mtvsrdd/mfvsrld because they were introduced in PowerISA v3.0, and > xscvspdpn/xscvdpspn are from v2.07. Fair enough, I suppose. > How about > > asm("mtvsrd 0, %2\n\t" > "mtvsrd 1, %3\n\t" > "xxmrghd 0, 0, 1\n\t" > INSN " 0, 0\n\t" > "mfvsrd %0, 0\n\t" > "xxswapd 0, 0\n\t" > "mfvsrd %1, 0\n\t" > : "=r" (th), "=r" (tl) > : "r" (bh), "r" (bl) > : "vs0", "vs1"); > > ? Looks good. r~
diff --git a/tests/tcg/ppc64le/non_signalling_xscv.c b/tests/tcg/ppc64le/non_signalling_xscv.c index 77f0703333..494e01864d 100644 --- a/tests/tcg/ppc64le/non_signalling_xscv.c +++ b/tests/tcg/ppc64le/non_signalling_xscv.c @@ -5,23 +5,24 @@ #define TEST(INSN, B_HI, B_LO, T_HI, T_LO) \ do { \ - __uint128_t t, b = B_HI; \ - b <<= 64; \ - b |= B_LO; \ - asm(INSN " %x0, %x1\n\t" \ - : "=wa" (t) \ - : "wa" (b)); \ + uint64_t th, tl, bh = B_HI, bl = B_LO; \ + asm("mtvsrd 0, %3\n\t" \ + "xxswapd 0, 0\n\t" \ + "mtvsrd 0, %2\n\t" \ + INSN " 0, 0\n\t" \ + "mfvsrd %0, 0\n\t" \ + "xxswapd 0, 0\n\t" \ + "mfvsrd %1, 0\n\t" \ + : "=r" (th), "=r" (tl) \ + : "r" (bh), "r" (bl) \ + : "vs0"); \ printf(INSN "(0x%016" PRIx64 "%016" PRIx64 ") = 0x%016" PRIx64 \ - "%016" PRIx64 "\n", (uint64_t)(b >> 64), (uint64_t)b, \ - (uint64_t)(t >> 64), (uint64_t)t); \ - assert((uint64_t)(t >> 64) == T_HI && (uint64_t)t == T_LO); \ + "%016" PRIx64 "\n", bh, bl, th, tl); \ + assert(th == T_HI && tl == T_LO); \ } while (0) int main(void) { -#ifndef __SIZEOF_INT128__ - puts("__uint128_t not available, skipping...\n"); -#else /* SNaN shouldn't be silenced */ TEST("xscvspdpn", 0x7fbfffff00000000ULL, 0x0, 0x7ff7ffffe0000000ULL, 0x0); TEST("xscvdpspn", 0x7ff7ffffffffffffULL, 0x0, 0x7fbfffff7fbfffffULL, 0x0); @@ -31,6 +32,6 @@ int main(void) * signifcand will return Infinity as the result. */ TEST("xscvdpspn", 0x7ff000001fffffffULL, 0x0, 0x7f8000007f800000ULL, 0x0); -#endif + return 0; }