diff mbox series

[4/4] target/ppc: move xscvqpdp to decodetree

Message ID 20211210141347.38603-5-victor.colombo@eldorado.org.br
State Superseded
Headers show
Series target/ppc: Fix VSX instructions register access | expand

Commit Message

Víctor Colombo Dec. 10, 2021, 2:13 p.m. UTC 
From: Matheus Ferst <matheus.ferst@eldorado.org.br>

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/fpu_helper.c             | 10 +++-------
 target/ppc/helper.h                 |  2 +-
 target/ppc/insn32.decode            |  4 ++++
 target/ppc/translate/vsx-impl.c.inc | 24 +++++++++++++-----------
 target/ppc/translate/vsx-ops.c.inc  |  1 -
 5 files changed, 21 insertions(+), 20 deletions(-)

Comments

Matheus K. Ferst Dec. 10, 2021, 4:19 p.m. UTC | #1 
On 10/12/2021 11:13, Victor Colombo wrote:
> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
> 
> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
> ---
>   target/ppc/fpu_helper.c             | 10 +++-------
>   target/ppc/helper.h                 |  2 +-
>   target/ppc/insn32.decode            |  4 ++++
>   target/ppc/translate/vsx-impl.c.inc | 24 +++++++++++++-----------
>   target/ppc/translate/vsx-ops.c.inc  |  1 -
>   5 files changed, 21 insertions(+), 20 deletions(-)

<snip>

> diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
> index ab5cb21f13..f8669cae42 100644
> --- a/target/ppc/translate/vsx-impl.c.inc
> +++ b/target/ppc/translate/vsx-impl.c.inc
> @@ -904,22 +904,24 @@ VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
>   VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
>   VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX)
>   
> -static void gen_xscvqpdp(DisasContext *ctx)
> +static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
>   {
> -    TCGv_i32 opc;
> +    TCGv_i32 ro;
>       TCGv_ptr xt, xb;
> -    if (unlikely(!ctx->vsx_enabled)) {
> -        gen_exception(ctx, POWERPC_EXCP_VSXU);
> -        return;
> -    }
> -    opc = tcg_const_i32(ctx->opcode);
>   
> -    xt = gen_vsr_ptr(rD(ctx->opcode) + 32);
> -    xb = gen_vsr_ptr(rB(ctx->opcode) + 32);
> -    gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
> -    tcg_temp_free_i32(opc);
> +    REQUIRE_INSNS_FLAGS2(ctx, ISA310);

It's actually ISA300. We'll send a v2 fixing this.
Richard Henderson Dec. 11, 2021, 5:07 p.m. UTC | #2 
On 12/10/21 8:19 AM, Matheus K. Ferst wrote:
> On 10/12/2021 11:13, Victor Colombo wrote:
>> From: Matheus Ferst <matheus.ferst@eldorado.org.br>
>>
>> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
>> ---
>>   target/ppc/fpu_helper.c             | 10 +++-------
>>   target/ppc/helper.h                 |  2 +-
>>   target/ppc/insn32.decode            |  4 ++++
>>   target/ppc/translate/vsx-impl.c.inc | 24 +++++++++++++-----------
>>   target/ppc/translate/vsx-ops.c.inc  |  1 -
>>   5 files changed, 21 insertions(+), 20 deletions(-)
> 
> <snip>
> 
>> diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
>> index ab5cb21f13..f8669cae42 100644
>> --- a/target/ppc/translate/vsx-impl.c.inc
>> +++ b/target/ppc/translate/vsx-impl.c.inc
>> @@ -904,22 +904,24 @@ VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
>>   VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
>>   VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX)
>> -static void gen_xscvqpdp(DisasContext *ctx)
>> +static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
>>   {
>> -    TCGv_i32 opc;
>> +    TCGv_i32 ro;
>>       TCGv_ptr xt, xb;
>> -    if (unlikely(!ctx->vsx_enabled)) {
>> -        gen_exception(ctx, POWERPC_EXCP_VSXU);
>> -        return;
>> -    }
>> -    opc = tcg_const_i32(ctx->opcode);
>> -    xt = gen_vsr_ptr(rD(ctx->opcode) + 32);
>> -    xb = gen_vsr_ptr(rB(ctx->opcode) + 32);
>> -    gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
>> -    tcg_temp_free_i32(opc);
>> +    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
> 
> It's actually ISA300. We'll send a v2 fixing this.

Yep.  With that,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
diff mbox series

Patch

diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index ad41ef1606..46f507604f 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2676,18 +2676,14 @@  VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
 VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i  + 1), 0)
 VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
 
-/*
- * xscvqpdp isn't using VSX_CVT_FP_TO_FP() because xscvqpdpo will be
- * added to this later.
- */
-void helper_xscvqpdp(CPUPPCState *env, uint32_t opcode,
-                     ppc_vsr_t *xt, ppc_vsr_t *xb)
+void helper_XSCVQPDP(CPUPPCState *env, uint32_t ro, ppc_vsr_t *xt,
+                     ppc_vsr_t *xb)
 {
     ppc_vsr_t t = { };
     float_status tstat;
 
     tstat = env->fp_status;
-    if (unlikely(Rc(opcode) != 0)) {
+    if (ro != 0) {
         tstat.float_rounding_mode = float_round_to_odd;
     }
 
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 12a3d5f269..ef5bdd38a7 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -400,7 +400,7 @@  DEF_HELPER_3(xscvdphp, void, env, vsr, vsr)
 DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr)
 DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr)
 DEF_HELPER_2(xscvdpspn, i64, env, i64)
-DEF_HELPER_4(xscvqpdp, void, env, i32, vsr, vsr)
+DEF_HELPER_4(XSCVQPDP, void, env, i32, vsr, vsr)
 DEF_HELPER_4(xscvqpsdz, void, env, i32, vsr, vsr)
 DEF_HELPER_4(xscvqpswz, void, env, i32, vsr, vsr)
 DEF_HELPER_4(xscvqpudz, void, env, i32, vsr, vsr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 759b2a9aa5..fd6bb13fa0 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -438,3 +438,7 @@  XSMAXCDP        111100 ..... ..... ..... 10000000 ...   @XX3
 XSMINCDP        111100 ..... ..... ..... 10001000 ...   @XX3
 XSMAXJDP        111100 ..... ..... ..... 10010000 ...   @XX3
 XSMINJDP        111100 ..... ..... ..... 10011000 ...   @XX3
+
+## VSX Binary Floating-Point Convert Instructions
+
+XSCVQPDP        111111 ..... 10100 ..... 1101000100 .   @X_tb_rc
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index ab5cb21f13..f8669cae42 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -904,22 +904,24 @@  VSX_CMP(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
 VSX_CMP(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
 VSX_CMP(xvcmpnesp, 0x0C, 0x0B, 0, PPC2_VSX)
 
-static void gen_xscvqpdp(DisasContext *ctx)
+static bool trans_XSCVQPDP(DisasContext *ctx, arg_X_tb_rc *a)
 {
-    TCGv_i32 opc;
+    TCGv_i32 ro;
     TCGv_ptr xt, xb;
-    if (unlikely(!ctx->vsx_enabled)) {
-        gen_exception(ctx, POWERPC_EXCP_VSXU);
-        return;
-    }
-    opc = tcg_const_i32(ctx->opcode);
 
-    xt = gen_vsr_ptr(rD(ctx->opcode) + 32);
-    xb = gen_vsr_ptr(rB(ctx->opcode) + 32);
-    gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
-    tcg_temp_free_i32(opc);
+    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+    REQUIRE_VSX(ctx);
+
+    ro = tcg_const_i32(a->rc);
+
+    xt = gen_avr_ptr(a->rt);
+    xb = gen_avr_ptr(a->rb);
+    gen_helper_XSCVQPDP(cpu_env, ro, xt, xb);
+    tcg_temp_free_i32(ro);
     tcg_temp_free_ptr(xt);
     tcg_temp_free_ptr(xb);
+
+    return true;
 }
 
 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type)                         \
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index f980bc1bae..c974324c4c 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -133,7 +133,6 @@  GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
 GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
 GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
 GEN_VSX_XFORM_300_EO(xscvdpqp, 0x04, 0x1A, 0x16, 0x00000001),
-GEN_VSX_XFORM_300_EO(xscvqpdp, 0x04, 0x1A, 0x14, 0x0),
 GEN_VSX_XFORM_300_EO(xscvqpsdz, 0x04, 0x1A, 0x19, 0x00000001),
 GEN_VSX_XFORM_300_EO(xscvqpswz, 0x04, 0x1A, 0x09, 0x00000001),
 GEN_VSX_XFORM_300_EO(xscvqpudz, 0x04, 0x1A, 0x11, 0x00000001),