diff mbox series

[v2,30/34] target/ppc: implemented XXSPLTI32DX

Message ID 20211029202424.175401-31-matheus.ferst@eldorado.org.br
State Superseded
Headers show
Series PowerISA v3.1 instruction batch | expand

Commit Message

Matheus K. Ferst Oct. 29, 2021, 8:24 p.m. UTC 
From: "Bruno Larsen (billionai)" <bruno.larsen@eldorado.org.br>

Implemented XXSPLTI32DX emulation using decodetree

Signed-off-by: Bruno Larsen (billionai) <bruno.larsen@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
v2:
- 8RR_D si field is now unsigned
- Implemented with two tcg_gen_st_i32
---
 target/ppc/insn64.decode            | 11 +++++++++++
 target/ppc/translate/vsx-impl.c.inc | 17 +++++++++++++++++
 2 files changed, 28 insertions(+)

Comments

Richard Henderson Oct. 30, 2021, 11:27 p.m. UTC | #1 
On 10/29/21 1:24 PM, matheus.ferst@eldorado.org.br wrote:
> From: "Bruno Larsen (billionai)"<bruno.larsen@eldorado.org.br>
> 
> Implemented XXSPLTI32DX emulation using decodetree
> 
> Signed-off-by: Bruno Larsen (billionai)<bruno.larsen@eldorado.org.br>
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
> v2:
> - 8RR_D si field is now unsigned
> - Implemented with two tcg_gen_st_i32
> ---
>   target/ppc/insn64.decode            | 11 +++++++++++
>   target/ppc/translate/vsx-impl.c.inc | 17 +++++++++++++++++
>   2 files changed, 28 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 880ac3edc7..134bc60c57 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -32,6 +32,14 @@ 
                 ...... ..... ra:5 ................       \
                 &PLS_D si=%pls_si rt=%rt_tsxp
 
+# Format 8RR:D
+%8rr_si         32:s16 0:16
+%8rr_xt         16:1 21:5
+&8RR_D_IX       xt ix si
+@8RR_D_IX       ...... .. .... .. .. ................ \
+                ...... ..... ... ix:1 . ................ \
+                &8RR_D_IX si=%8rr_si xt=%8rr_xt
+
 ### Fixed-Point Load Instructions
 
 PLBZ            000001 10 0--.-- .................. \
@@ -156,3 +164,6 @@  PLXVP           000001 00 0--.-- .................. \
                 111010 ..... ..... ................     @8LS_D_TSXP
 PSTXVP          000001 00 0--.-- .................. \
                 111110 ..... ..... ................     @8LS_D_TSXP
+
+XXSPLTI32DX     000001 01 0000 -- -- ................ \
+                100000 ..... 000 .. ................    @8RR_D_IX
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index b64b965255..552f05bbda 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1466,6 +1466,23 @@  static bool trans_XXSPLTIB(DisasContext *ctx, arg_X_imm8 *a)
     return true;
 }
 
+static bool trans_XXSPLTI32DX(DisasContext *ctx, arg_8RR_D_IX *a)
+{
+    TCGv_i32 imm;
+
+    REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+    REQUIRE_VSX(ctx);
+
+    imm = tcg_constant_i32(a->si);
+
+    tcg_gen_st_i32(imm, cpu_env,
+        offsetof(CPUPPCState, vsr[a->xt].VsrW(0 + a->ix)));
+    tcg_gen_st_i32(imm, cpu_env,
+        offsetof(CPUPPCState, vsr[a->xt].VsrW(2 + a->ix)));
+
+    return true;
+}
+
 static void gen_xxsldwi(DisasContext *ctx)
 {
     TCGv_i64 xth, xtl;