From patchwork Mon Oct 25 19:11:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luis Fernando Fujita Pires X-Patchwork-Id: 1545915 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4HdQ3F69Q1z9sX3 for ; Tue, 26 Oct 2021 06:28:09 +1100 (AEDT) Received: from localhost ([::1]:34338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mf5df-0000ED-3a for incoming@patchwork.ozlabs.org; Mon, 25 Oct 2021 15:28:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42036) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mf5Px-0000pj-5W; Mon, 25 Oct 2021 15:13:57 -0400 Received: from [201.28.113.2] (port=13660 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mf5Pv-0000Ju-Gj; Mon, 25 Oct 2021 15:13:56 -0400 Received: from power9a ([10.10.71.235]) by outlook.eldorado.org.br with Microsoft SMTPSVC(8.5.9600.16384); Mon, 25 Oct 2021 16:12:27 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by power9a (Postfix) with ESMTP id 22926800145; Mon, 25 Oct 2021 16:12:27 -0300 (-03) From: Luis Pires To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v4 08/19] target/ppc: Implement DCFFIXQQ Date: Mon, 25 Oct 2021 16:11:43 -0300 Message-Id: <20211025191154.350831-9-luis.pires@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211025191154.350831-1-luis.pires@eldorado.org.br> References: <20211025191154.350831-1-luis.pires@eldorado.org.br> MIME-Version: 1.0 X-OriginalArrivalTime: 25 Oct 2021 19:12:27.0454 (UTC) FILETIME=[3FFD65E0:01D7C9D4] X-Host-Lookup-Failed: Reverse DNS lookup failed for 201.28.113.2 (failed) Received-SPF: pass client-ip=201.28.113.2; envelope-from=luis.pires@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luis Pires , richard.henderson@linaro.org, groug@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-ppc" Implement the following PowerISA v3.1 instruction: dcffixqq: DFP Convert From Fixed Quadword Quad Signed-off-by: Luis Pires Reviewed-by: Richard Henderson --- target/ppc/dfp_helper.c | 12 ++++++++++++ target/ppc/helper.h | 1 + target/ppc/insn32.decode | 8 ++++++++ target/ppc/translate.c | 5 +++++ target/ppc/translate/dfp-impl.c.inc | 17 +++++++++++++++++ 5 files changed, 43 insertions(+) diff --git a/target/ppc/dfp_helper.c b/target/ppc/dfp_helper.c index 07341a69f5..6b837c4450 100644 --- a/target/ppc/dfp_helper.c +++ b/target/ppc/dfp_helper.c @@ -970,6 +970,18 @@ static void CFFIX_PPs(struct PPC_DFP *dfp) DFP_HELPER_CFFIX(dcffix, 64) DFP_HELPER_CFFIX(dcffixq, 128) +void helper_DCFFIXQQ(CPUPPCState *env, ppc_fprp_t *t, ppc_avr_t *b) +{ + struct PPC_DFP dfp; + + dfp_prepare_decimal128(&dfp, NULL, NULL, env); + decNumberFromInt128(&dfp.t, (uint64_t)b->VsrD(1), (int64_t)b->VsrD(0)); + dfp_finalize_decimal128(&dfp); + CFFIX_PPs(&dfp); + + set_dfp128(t, &dfp.vt); +} + #define DFP_HELPER_CTFIX(op, size) \ void helper_##op(CPUPPCState *env, ppc_fprp_t *t, ppc_fprp_t *b) \ { \ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 4076aa281e..fff7bd46ad 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -734,6 +734,7 @@ DEF_HELPER_3(drsp, void, env, fprp, fprp) DEF_HELPER_3(drdpq, void, env, fprp, fprp) DEF_HELPER_3(dcffix, void, env, fprp, fprp) DEF_HELPER_3(dcffixq, void, env, fprp, fprp) +DEF_HELPER_3(DCFFIXQQ, void, env, fprp, avr) DEF_HELPER_3(dctfix, void, env, fprp, fprp) DEF_HELPER_3(dctfixq, void, env, fprp, fprp) DEF_HELPER_4(ddedpd, void, env, fprp, fprp, i32) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 9fd8d6b817..92ea2d0739 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -43,6 +43,10 @@ &X_bfl bf l:bool ra rb @X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl +&X_frtp_vrb frtp vrb +%x_frtp 22:4 !function=times_2 +@X_frtp_vrb ...... ....0 ..... vrb:5 .......... . &X_frtp_vrb frtp=%x_frtp + ### Fixed-Point Load Instructions LBZ 100010 ..... ..... ................ @D @@ -121,6 +125,10 @@ SETBCR 011111 ..... ..... ----- 0110100000 - @X_bi SETNBC 011111 ..... ..... ----- 0111000000 - @X_bi SETNBCR 011111 ..... ..... ----- 0111100000 - @X_bi +### Decimal Floating-Point Conversion Instructions + +DCFFIXQQ 111111 ..... 00000 ..... 1111100010 - @X_frtp_vrb + ## Vector Bit Manipulation Instruction VCFUGED 000100 ..... ..... ..... 10101001101 @VX diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 48a484eef6..6224cb3211 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7438,6 +7438,11 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high) /* * Helpers for decodetree used by !function for decoding arguments. */ +static int times_2(DisasContext *ctx, int x) +{ + return x * 2; +} + static int times_4(DisasContext *ctx, int x) { return x * 4; diff --git a/target/ppc/translate/dfp-impl.c.inc b/target/ppc/translate/dfp-impl.c.inc index 6c556dc2e1..d5b66567a6 100644 --- a/target/ppc/translate/dfp-impl.c.inc +++ b/target/ppc/translate/dfp-impl.c.inc @@ -230,3 +230,20 @@ GEN_DFP_T_FPR_I32_Rc(dscriq, rA, DCM) #undef GEN_DFP_T_A_B_I32_Rc #undef GEN_DFP_T_B_Rc #undef GEN_DFP_T_FPR_I32_Rc + +static bool trans_DCFFIXQQ(DisasContext *ctx, arg_DCFFIXQQ *a) +{ + TCGv_ptr rt, rb; + + REQUIRE_INSNS_FLAGS2(ctx, DFP); + REQUIRE_FPU(ctx); + REQUIRE_VECTOR(ctx); + + rt = gen_fprp_ptr(a->frtp); + rb = gen_avr_ptr(a->vrb); + gen_helper_DCFFIXQQ(cpu_env, rt, rb); + tcg_temp_free_ptr(rt); + tcg_temp_free_ptr(rb); + + return true; +}