docs: Minor updates on the powernv documentation.

From: Leonardo Garcia <lagarcia@br.ibm.com>

Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
---
 docs/system/ppc/powernv.rst | 56 +++++++++++++++++++------------------
 1 file changed, 29 insertions(+), 27 deletions(-)

On 11/17/21 21:16, lagarcia@linux.ibm.com wrote:
> From: Leonardo Garcia <lagarcia@br.ibm.com>
> 
> Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
> ---
>   docs/system/ppc/powernv.rst | 56 +++++++++++++++++++------------------
>   1 file changed, 29 insertions(+), 27 deletions(-)
> 
> diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst
> index 86186b7d2c..907c4ce4f9 100644
> --- a/docs/system/ppc/powernv.rst
> +++ b/docs/system/ppc/powernv.rst
> @@ -1,7 +1,7 @@
> -PowerNV family boards (``powernv8``, ``powernv9``)
> +PowerNV family boards (``powernv8``, ``powernv9``, ``power10``)

powernv10.

And I still haven't resent the XIVE2/PHB5 patches to enable full support.

>   ==================================================================
>   
> -PowerNV (as Non-Virtualized) is the "baremetal" platform using the
> +PowerNV (as Non-Virtualized) is the "bare metal" platform using the
>   OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can
>   be used as an hypervisor OS, running KVM guests, or simply as a host
>   OS.
> @@ -15,17 +15,15 @@ beyond the scope of what QEMU addresses today.
>   Supported devices
>   -----------------
>   
> - * Multi processor support for POWER8, POWER8NVL and POWER9.
> - * XSCOM, serial communication sideband bus to configure chiplets
> - * Simple LPC Controller
> - * Processor Service Interface (PSI) Controller
> - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9)
> - * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge
> - * Simple OCC is an on-chip microcontroller used for power management
> -   tasks
> - * iBT device to handle BMC communication, with the internal BMC
> -   simulator provided by QEMU or an external BMC such as an Aspeed
> -   QEMU machine.
> + * Multi processor support for POWER8, POWER8NVL and Power9.

s/Power9/POWER9/ right ? I am starting to doubt :)

> + * XSCOM, serial communication sideband bus to configure chiplets.
> + * Simple LPC Controller.
> + * Processor Service Interface (PSI) Controller.
> + * Interrupt Controller, XICS (POWER8) and XIVE (Power9) and XIVE2 (Power10).
> + * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
> + * Simple OCC is an on-chip micro-controller used for power management tasks.
> + * iBT device to handle BMC communication, with the internal BMC simulator
> +   provided by QEMU or an external BMC such as an Aspeed QEMU machine.
>    * PNOR containing the different firmware partitions.
>   
>   Missing devices
> @@ -33,27 +31,25 @@ Missing devices
>   
>   A lot is missing, among which :
>   
> - * POWER10 processor
> - * XIVE2 (POWER10) interrupt controller
> - * I2C controllers (yet to be merged)
> - * NPU/NPU2/NPU3 controllers
> - * EEH support for PCIe Host bridge controllers
> - * NX controller
> - * VAS controller
> - * chipTOD (Time Of Day)
> + * I2C controllers (yet to be merged).
> + * NPU/NPU2/NPU3 controllers.
> + * EEH support for PCIe Host bridge controllers.
> + * NX controller.
> + * VAS controller.
> + * chipTOD (Time Of Day).
>    * Self Boot Engine (SBE).
> - * FSI bus
> + * FSI bus.
>   
>   Firmware
>   --------
>   
>   The OPAL firmware (OpenPower Abstraction Layer) for OpenPower systems
>   includes the runtime services ``skiboot`` and the bootloader kernel and
> -initramfs ``skiroot``. Source code can be found on GitHub:
> +initramfs ``skiroot``. Source code can be found on the `OpenPOWER account at
> +GitHub <https://github.com/open-power>`_.
>   
> -  https://github.com/open-power.
> -
> -Prebuilt images of ``skiboot`` and ``skiroot`` are made available on the `OpenPOWER <https://github.com/open-power/op-build/releases/>`__ site.
> +Prebuilt images of ``skiboot`` and ``skiroot`` are made available on the
> +`OpenPOWER <https://github.com/open-power/op-build/releases/>`__ site.
>   
>   QEMU includes a prebuilt image of ``skiboot`` which is updated when a
>   more recent version is required by the models.
> @@ -83,6 +79,7 @@ and a SATA disk :
>   
>   Complex PCIe configuration
>   ~~~~~~~~~~~~~~~~~~~~~~~~~~
> +
>   Six PHBs are defined per chip (POWER9) but no default PCI layout is
>   provided (to be compatible with libvirt). One PCI device can be added
>   on any of the available PCIe slots using command line options such as:
> @@ -157,7 +154,7 @@ one on the command line :
>   The files `palmetto-SDR.bin <http://www.kaod.org/qemu/powernv/palmetto-SDR.bin>`__
>   and `palmetto-FRU.bin <http://www.kaod.org/qemu/powernv/palmetto-FRU.bin>`__
>   define a Sensor Data Record repository and a Field Replaceable Unit
> -inventory for a palmetto BMC. They can be used to extend the QEMU BMC
> +inventory for a Palmetto BMC. They can be used to extend the QEMU BMC
>   simulator.
>   
>   .. code-block:: bash
> @@ -190,3 +187,8 @@ CAVEATS
>   
>    * No support for multiple HW threads (SMT=1). Same as pseries.
>    * CPU can hang when doing intensive I/Os. Use ``-append powersave=off`` in that case.

The last caveat is not true. I found the issue since in the decrementer
model.

Thanks

C.

> +
> +Maintainer contact information
> +------------------------------
> +
> +Cédric Le Goater <clg@kaod.org>
> \ No newline at end of file
>

On 11/18/21 06:03, Cédric Le Goater wrote:
> On 11/17/21 21:16, lagarcia@linux.ibm.com wrote:
>> From: Leonardo Garcia <lagarcia@br.ibm.com>
>>
>> Signed-off-by: Leonardo Garcia <lagarcia@br.ibm.com>
>> ---
>>   docs/system/ppc/powernv.rst | 56 +++++++++++++++++++------------------
>>   1 file changed, 29 insertions(+), 27 deletions(-)
>>
>> diff --git a/docs/system/ppc/powernv.rst b/docs/system/ppc/powernv.rst
>> index 86186b7d2c..907c4ce4f9 100644
>> --- a/docs/system/ppc/powernv.rst
>> +++ b/docs/system/ppc/powernv.rst
>> @@ -1,7 +1,7 @@
>> -PowerNV family boards (``powernv8``, ``powernv9``)
>> +PowerNV family boards (``powernv8``, ``powernv9``, ``power10``)
>
> powernv10.
>
> And I still haven't resent the XIVE2/PHB5 patches to enable full support.
>
>>   ==================================================================
>>   -PowerNV (as Non-Virtualized) is the "baremetal" platform using the
>> +PowerNV (as Non-Virtualized) is the "bare metal" platform using the
>>   OPAL firmware. It runs Linux on IBM and OpenPOWER systems and it can
>>   be used as an hypervisor OS, running KVM guests, or simply as a host
>>   OS.
>> @@ -15,17 +15,15 @@ beyond the scope of what QEMU addresses today.
>>   Supported devices
>>   -----------------
>>   - * Multi processor support for POWER8, POWER8NVL and POWER9.
>> - * XSCOM, serial communication sideband bus to configure chiplets
>> - * Simple LPC Controller
>> - * Processor Service Interface (PSI) Controller
>> - * Interrupt Controller, XICS (POWER8) and XIVE (POWER9)
>> - * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge
>> - * Simple OCC is an on-chip microcontroller used for power management
>> -   tasks
>> - * iBT device to handle BMC communication, with the internal BMC
>> -   simulator provided by QEMU or an external BMC such as an Aspeed
>> -   QEMU machine.
>> + * Multi processor support for POWER8, POWER8NVL and Power9.
>
> s/Power9/POWER9/ right ? I am starting to doubt :)


Well... <sigh>...

According to IBM new branding rules (I wasn't able to find any external
documents on this but we were asked to use it externally), the processor
name is now Power instead of POWER. As the document I have access to
only references Power9 and Power10, I am interpreting this as "don't
mess with old names", specially as I don't want to start rewriting
documents and comments because of these marketing changes of humor. TBH,
I am OK either way.

I will include the other suggestions in a new patch and resubmit.

Cheers,

Leo


>
>> + * XSCOM, serial communication sideband bus to configure chiplets.
>> + * Simple LPC Controller.
>> + * Processor Service Interface (PSI) Controller.
>> + * Interrupt Controller, XICS (POWER8) and XIVE (Power9) and XIVE2
>> (Power10).
>> + * POWER8 PHB3 PCIe Host bridge and POWER9 PHB4 PCIe Host bridge.
>> + * Simple OCC is an on-chip micro-controller used for power
>> management tasks.
>> + * iBT device to handle BMC communication, with the internal BMC
>> simulator
>> +   provided by QEMU or an external BMC such as an Aspeed QEMU machine.
>>    * PNOR containing the different firmware partitions.
>>     Missing devices
>> @@ -33,27 +31,25 @@ Missing devices
>>     A lot is missing, among which :
>>   - * POWER10 processor
>> - * XIVE2 (POWER10) interrupt controller
>> - * I2C controllers (yet to be merged)
>> - * NPU/NPU2/NPU3 controllers
>> - * EEH support for PCIe Host bridge controllers
>> - * NX controller
>> - * VAS controller
>> - * chipTOD (Time Of Day)
>> + * I2C controllers (yet to be merged).
>> + * NPU/NPU2/NPU3 controllers.
>> + * EEH support for PCIe Host bridge controllers.
>> + * NX controller.
>> + * VAS controller.
>> + * chipTOD (Time Of Day).
>>    * Self Boot Engine (SBE).
>> - * FSI bus
>> + * FSI bus.
>>     Firmware
>>   --------
>>     The OPAL firmware (OpenPower Abstraction Layer) for OpenPower
>> systems
>>   includes the runtime services ``skiboot`` and the bootloader kernel
>> and
>> -initramfs ``skiroot``. Source code can be found on GitHub:
>> +initramfs ``skiroot``. Source code can be found on the `OpenPOWER
>> account at
>> +GitHub <https://github.com/open-power>`_.
>>   -  https://github.com/open-power.
>> -
>> -Prebuilt images of ``skiboot`` and ``skiroot`` are made available on
>> the `OpenPOWER <https://github.com/open-power/op-build/releases/>`__
>> site.
>> +Prebuilt images of ``skiboot`` and ``skiroot`` are made available on
>> the
>> +`OpenPOWER <https://github.com/open-power/op-build/releases/>`__ site.
>>     QEMU includes a prebuilt image of ``skiboot`` which is updated
>> when a
>>   more recent version is required by the models.
>> @@ -83,6 +79,7 @@ and a SATA disk :
>>     Complex PCIe configuration
>>   ~~~~~~~~~~~~~~~~~~~~~~~~~~
>> +
>>   Six PHBs are defined per chip (POWER9) but no default PCI layout is
>>   provided (to be compatible with libvirt). One PCI device can be added
>>   on any of the available PCIe slots using command line options such as:
>> @@ -157,7 +154,7 @@ one on the command line :
>>   The files `palmetto-SDR.bin
>> <http://www.kaod.org/qemu/powernv/palmetto-SDR.bin>`__
>>   and `palmetto-FRU.bin
>> <http://www.kaod.org/qemu/powernv/palmetto-FRU.bin>`__
>>   define a Sensor Data Record repository and a Field Replaceable Unit
>> -inventory for a palmetto BMC. They can be used to extend the QEMU BMC
>> +inventory for a Palmetto BMC. They can be used to extend the QEMU BMC
>>   simulator.
>>     .. code-block:: bash
>> @@ -190,3 +187,8 @@ CAVEATS
>>      * No support for multiple HW threads (SMT=1). Same as pseries.
>>    * CPU can hang when doing intensive I/Os. Use ``-append
>> powersave=off`` in that case.
>
> The last caveat is not true. I found the issue since in the decrementer
> model.
>
> Thanks
>
> C.
>
>> +
>> +Maintainer contact information
>> +------------------------------
>> +
>> +Cédric Le Goater <clg@kaod.org>
>> \ No newline at end of file
>>
>
>