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[v3,0/3] target/ppc: Update vector insns to use 128 bit

Message ID 20240709114341.152175-1-rathc@linux.ibm.com
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Series target/ppc: Update vector insns to use 128 bit | expand

Message

Chinmay Rath July 9, 2024, 11:43 a.m. UTC 
Updating a bunch of VMX and VSX storage access instructions to use
tcg_gen_qemu_ld/st_i128 instead of using tcg_gen_qemu_ld/st_i64 in
succession; as suggested by Richard, in my decodetree patches.
Plus some minor clean-ups to facilitate the above in case of VMX insns.

Change log:

v3 : Rectified EA increment from 8 to 16 for paired insns in patch 3/3,
as pointed by Richard.
Retained his 'Reviewed-by' for all patches, after the correction.

v2 : Applied IFALIGN_PAIR memop changes in patches 2/3 and 3/3,
based on review comments by Richard.
https://lore.kernel.org/qemu-devel/20240630120157.259233-1-rathc@linux.ibm.com/

v3 : https://lore.kernel.org/qemu-devel/20240621114604.868415-1-rathc@linux.ibm.com/

Chinmay Rath (3):
  target/ppc: Move get/set_avr64 functions to vmx-impl.c.inc.
  target/ppc: Update VMX storage access insns to use
    tcg_gen_qemu_ld/st_i128.
  target/ppc : Update VSX storage access insns to use tcg_gen_qemu
    _ld/st_i128.

 target/ppc/translate.c              | 10 ----
 target/ppc/translate/vmx-impl.c.inc | 52 +++++++++++---------
 target/ppc/translate/vsx-impl.c.inc | 74 +++++++++++++----------------
 3 files changed, 63 insertions(+), 73 deletions(-)