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[v4,00/24] ppc: QOM'ify 405 board

Message ID 20220809153904.485018-1-clg@kaod.org
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Series ppc: QOM'ify 405 board | expand

Message

Cédric Le Goater Aug. 9, 2022, 3:38 p.m. UTC
Hello,

Here is large series QOM'ifying the PPC405 board. It introduces a new
generic machine and SoC models, converts the current device models to
QOM and populates the SoC. The process is quite mechanical without too
much issues to handle. The noisy part is the initial patch introducing
the SoC realize routine.

Thanks,

C.

Changes in v4 :

 - Attempt to QOM'ify SDRAM controller, with 2 initialized banks at
   the SoC level 
 - Report errors to the user for invalid RAM config
 - Moved CPU reset in PPC405 model
 - user_creatable comments
 - Renamed FPGA device model
 - Various small cleanups

Changes in v3 :

 - New device model Ppc4xxDcrDeviceState
 - Removal of ppc4xx_mal_init(), ppc4xx_plb_init() and ppc405_ebc_init()
 - Fixes for some reset issues
 - Kept 2 RAM banks at the Soc level but only one is initialized.
 - Moved SRAM under the machine. It's not part of the SoC according
   to the 405 specs

Changes in v2 :

 - docs/about/removed-features.rst update
 - Fix compile breakage (uic)
 - Fix CPU reset, which breaking u-boot boot
 - Changed prefix of memory regions to "ppc405"
 - Reduced the number of RAM banks to 1. Second was a dummy one to
   please ppc405ep_init()

Cédric Le Goater (24):
  ppc/ppc405: Remove taihu machine
  ppc/ppc405: Introduce a PPC405 generic machine
  ppc/ppc405: Move devices under the ref405ep machine
  ppc/ppc405: Move SRAM under the ref405ep machine
  ppc/ppc405: Introduce a PPC405 SoC
  ppc/ppc405: Start QOMification of the SoC
  ppc/ppc405: QOM'ify CPU
  ppc/ppc4xx: Introduce a DCR device model
  ppc/ppc405: QOM'ify CPC
  ppc/ppc405: QOM'ify GPT
  ppc/ppc405: QOM'ify OCM
  ppc/ppc405: QOM'ify GPIO
  ppc/ppc405: QOM'ify DMA
  ppc/ppc405: QOM'ify EBC
  ppc/ppc405: QOM'ify OPBA
  ppc/ppc405: QOM'ify POB
  ppc/ppc405: QOM'ify PLB
  ppc/ppc405: QOM'ify MAL
  ppc/ppc405: QOM'ify FPGA
  ppc/ppc405: Use an embedded PPCUIC model in SoC state
  ppc/ppc405: Use an explicit I2C object
  ppc/ppc4xx: Fix sdram trace events
  ppc/ppc405: QOM'ify SDRAM
  ppc/ppc405: Add check on minimum RAM size

 docs/about/deprecated.rst       |   9 -
 docs/about/removed-features.rst |   6 +
 docs/system/ppc/embedded.rst    |   1 -
 hw/ppc/ppc405.h                 | 196 +++++++-
 include/hw/ppc/ppc4xx.h         |  82 ++-
 hw/ppc/ppc405_boards.c          | 381 ++++----------
 hw/ppc/ppc405_uc.c              | 859 +++++++++++++++++---------------
 hw/ppc/ppc4xx_devs.c            | 326 +++++++-----
 hw/ppc/sam460ex.c               |  24 +-
 MAINTAINERS                     |   2 +-
 hw/ppc/trace-events             |   3 -
 11 files changed, 1042 insertions(+), 847 deletions(-)

Comments

Daniel Henrique Barboza Aug. 11, 2022, 8:24 a.m. UTC | #1
Cedric,

I pushed patches 1-7 to gitlab.com/danielhb/qemu/tree/ppc-7.2. This
way you have 7 less patches to worry about for the next versions.


Thanks,

Daniel


On 8/9/22 12:38, Cédric Le Goater wrote:
> Hello,
> 
> Here is large series QOM'ifying the PPC405 board. It introduces a new
> generic machine and SoC models, converts the current device models to
> QOM and populates the SoC. The process is quite mechanical without too
> much issues to handle. The noisy part is the initial patch introducing
> the SoC realize routine.
> 
> Thanks,
> 
> C.
> 
> Changes in v4 :
> 
>   - Attempt to QOM'ify SDRAM controller, with 2 initialized banks at
>     the SoC level
>   - Report errors to the user for invalid RAM config
>   - Moved CPU reset in PPC405 model
>   - user_creatable comments
>   - Renamed FPGA device model
>   - Various small cleanups
> 
> Changes in v3 :
> 
>   - New device model Ppc4xxDcrDeviceState
>   - Removal of ppc4xx_mal_init(), ppc4xx_plb_init() and ppc405_ebc_init()
>   - Fixes for some reset issues
>   - Kept 2 RAM banks at the Soc level but only one is initialized.
>   - Moved SRAM under the machine. It's not part of the SoC according
>     to the 405 specs
> 
> Changes in v2 :
> 
>   - docs/about/removed-features.rst update
>   - Fix compile breakage (uic)
>   - Fix CPU reset, which breaking u-boot boot
>   - Changed prefix of memory regions to "ppc405"
>   - Reduced the number of RAM banks to 1. Second was a dummy one to
>     please ppc405ep_init()
> 
> Cédric Le Goater (24):
>    ppc/ppc405: Remove taihu machine
>    ppc/ppc405: Introduce a PPC405 generic machine
>    ppc/ppc405: Move devices under the ref405ep machine
>    ppc/ppc405: Move SRAM under the ref405ep machine
>    ppc/ppc405: Introduce a PPC405 SoC
>    ppc/ppc405: Start QOMification of the SoC
>    ppc/ppc405: QOM'ify CPU
>    ppc/ppc4xx: Introduce a DCR device model
>    ppc/ppc405: QOM'ify CPC
>    ppc/ppc405: QOM'ify GPT
>    ppc/ppc405: QOM'ify OCM
>    ppc/ppc405: QOM'ify GPIO
>    ppc/ppc405: QOM'ify DMA
>    ppc/ppc405: QOM'ify EBC
>    ppc/ppc405: QOM'ify OPBA
>    ppc/ppc405: QOM'ify POB
>    ppc/ppc405: QOM'ify PLB
>    ppc/ppc405: QOM'ify MAL
>    ppc/ppc405: QOM'ify FPGA
>    ppc/ppc405: Use an embedded PPCUIC model in SoC state
>    ppc/ppc405: Use an explicit I2C object
>    ppc/ppc4xx: Fix sdram trace events
>    ppc/ppc405: QOM'ify SDRAM
>    ppc/ppc405: Add check on minimum RAM size
> 
>   docs/about/deprecated.rst       |   9 -
>   docs/about/removed-features.rst |   6 +
>   docs/system/ppc/embedded.rst    |   1 -
>   hw/ppc/ppc405.h                 | 196 +++++++-
>   include/hw/ppc/ppc4xx.h         |  82 ++-
>   hw/ppc/ppc405_boards.c          | 381 ++++----------
>   hw/ppc/ppc405_uc.c              | 859 +++++++++++++++++---------------
>   hw/ppc/ppc4xx_devs.c            | 326 +++++++-----
>   hw/ppc/sam460ex.c               |  24 +-
>   MAINTAINERS                     |   2 +-
>   hw/ppc/trace-events             |   3 -
>   11 files changed, 1042 insertions(+), 847 deletions(-)
>
Cédric Le Goater Aug. 11, 2022, 8:33 a.m. UTC | #2
On 8/11/22 10:24, Daniel Henrique Barboza wrote:
> Cedric,
> 
> I pushed patches 1-7 to gitlab.com/danielhb/qemu/tree/ppc-7.2. This
> way you have 7 less patches to worry about for the next versions.

Thanks Daniel,

C.