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Mon, 20 Dec 2021 18:19:12 GMT Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 247D2C6055; Mon, 20 Dec 2021 18:19:12 +0000 (GMT) Received: from b03ledav006.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AA4FFC6062; Mon, 20 Dec 2021 18:19:10 +0000 (GMT) Received: from farosas.linux.ibm.com.com (unknown [9.211.60.53]) by b03ledav006.gho.boulder.ibm.com (Postfix) with ESMTP; Mon, 20 Dec 2021 18:19:10 +0000 (GMT) From: Fabiano Rosas To: qemu-devel@nongnu.org Subject: [RFC v2 00/12] target/ppc: powerpc_excp improvements Date: Mon, 20 Dec 2021 15:18:51 -0300 Message-Id: <20211220181903.3456898-1-farosas@linux.ibm.com> X-Mailer: git-send-email 2.33.1 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: cUVBANxfyZ4UTOyTHCTw6UIldPQ6O4Om X-Proofpoint-ORIG-GUID: UPKcQ7sYcpzP-_GCZOgrJVICaHpSTjRG X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2021-12-20_08,2021-12-20_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 malwarescore=0 spamscore=0 suspectscore=0 bulkscore=0 clxscore=1015 impostorscore=0 mlxlogscore=493 lowpriorityscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2112200101 Received-SPF: pass client-ip=148.163.158.5; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-ppc@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-ppc-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-ppc" This changed a lot since v1, basically what remains is the idea that we want to have some sort of array of interrupts and some sort of separation between processors. At the end of this series we'll have: - One file with all interrupt implementations (interrupts.c); - Separate files for each major group of CPUs (book3s, booke, 32bits). Only interrupt code for now, but we could bring pieces of cpu_init into them; - Four separate interrupt arrays, one for each of the above groups plus KVM. - powerpc_excp calls into the individual files and from there we dispatch according to what is available in the interrupts array. Please comment, Thanks. v1: https://lists.nongnu.org/archive/html/qemu-ppc/2021-06/msg00026.html Fabiano Rosas (12): target/ppc: powerpc_excp: Set alternate SRRs directly target/ppc: powerpc_excp: Set vector earlier target/ppc: powerpc_excp: Move system call vectored code together target/ppc: powerpc_excp: Stop passing excp_model around target/ppc: powerpc_excp: Standardize arguments to interrupt code target/ppc: Extract interrupt routines into a new file target/ppc: Introduce PPCInterrupt target/ppc: Remove unimplemented interrupt code target/ppc: Use common code for Hypervisor interrupts target/ppc: Split powerpc_excp into book3s, booke and 32 bit target/ppc: Create new files for book3s, booke and ppc32 exception code target/ppc: Do not enable all interrupts when running KVM target/ppc/cpu.h | 2 + target/ppc/excp_helper.c | 862 ++------------------------------------- target/ppc/interrupts.c | 521 +++++++++++++++++++++++ target/ppc/intr-book3s.c | 383 +++++++++++++++++ target/ppc/intr-booke.c | 152 +++++++ target/ppc/intr-ppc32.c | 159 ++++++++ target/ppc/meson.build | 4 + target/ppc/ppc_intr.h | 62 +++ target/ppc/tcg-stub.c | 6 + 9 files changed, 1323 insertions(+), 828 deletions(-) create mode 100644 target/ppc/interrupts.c create mode 100644 target/ppc/intr-book3s.c create mode 100644 target/ppc/intr-booke.c create mode 100644 target/ppc/intr-ppc32.c create mode 100644 target/ppc/ppc_intr.h