From patchwork Wed Jan 11 20:19:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artyom Tarasenko X-Patchwork-Id: 714015 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3tzMQl5XHTz9sCM for ; Thu, 12 Jan 2017 08:26:39 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="HH0igfEi"; dkim-atps=neutral Received: from localhost ([::1]:57247 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cRQPl-000746-Fg for incoming@patchwork.ozlabs.org; Wed, 11 Jan 2017 16:26:37 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55249) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cRPOg-00077W-Q9 for qemu-devel@nongnu.org; Wed, 11 Jan 2017 15:21:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cRPOf-0001U3-W6 for qemu-devel@nongnu.org; Wed, 11 Jan 2017 15:21:26 -0500 Received: from mail-wm0-x241.google.com ([2a00:1450:400c:c09::241]:35323) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cRPOf-0001Sx-Pm for qemu-devel@nongnu.org; Wed, 11 Jan 2017 15:21:25 -0500 Received: by mail-wm0-x241.google.com with SMTP id l2so570795wml.2 for ; Wed, 11 Jan 2017 12:21:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=0PObsB0fM7blXbr2AdN1V8UguEJiCdBVJBy/nrm91Tg=; b=HH0igfEia++aj3JzUf4NAwTP7iInDwO+r6JtUIrhhBV4rSUNy/ol9KJl+JeVQ5oRsf lr/ZI8chuGgaXNx2UCfjGBcVQ+erUOsc2D2a+VOb3c9phtceopH/4FpwGDuujiJk3IqK rrGRNP1sg1IhjWwKZGv/c5nfMAG64G1h9T3R02q2EbeN5VvG7qFr4KARKfbzQw+HjJtc halbmCAhNQPfbCkdNoMRT4InaI9Z4GYSaxrFidva8UPHdaT6DZcYk2+/1Wm0P23u7jRZ rbg0AQLZqqQcgNzIwWfqc/Z78+7+ErF56s6Yg1QMNd6QvJCtkq0Wo5s6SLATcF4McBtR czhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:in-reply-to:references; bh=0PObsB0fM7blXbr2AdN1V8UguEJiCdBVJBy/nrm91Tg=; b=RUbzi4nQmTKAhnPnB0y4AlH/+1KK20rV57T+vaj/kAlkokCo7pXeozk+lmcnogYsV4 GHM+a9u38wMeSdJ7+fxGrAQ/VrRR5/clZVv8aOs7TuliofM2aur1TodsVDMW/WN24bd5 Na4ORUftNDag5f5KH9U9cAnysD95KdFgGkGdUrTYQ2tqDEPO2M7SjS4E1c8oz1ex56qr OC13U1gUBDDoi4ctLxe/qxQg9ro6pNl18SFXAyru1ezkruFFba4hPXVnB+Kp+xffiA51 mnsyx8nhV8eUS8owv/e8PxZdM5+OcR8NBk3rEqsUXvlo1KtpnLHQzTf40gdh/u6F6fm6 ixGg== X-Gm-Message-State: AIkVDXIgAygCwJi5J7uKs5sodK9Jkg9hcJQLB/cGtlsbY553e4eeQ1Na8B9B8OLfOA3iyA== X-Received: by 10.28.178.142 with SMTP id b136mr6659266wmf.69.1484166084836; Wed, 11 Jan 2017 12:21:24 -0800 (PST) Received: from localhost (x55b4b54a.dyn.telefonica.de. [85.180.181.74]) by smtp.gmail.com with ESMTPSA id y127sm6186493wmg.12.2017.01.11.12.21.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Jan 2017 12:21:23 -0800 (PST) From: Artyom Tarasenko To: qemu-devel@nongnu.org Date: Wed, 11 Jan 2017 21:19:58 +0100 Message-Id: X-Mailer: git-send-email 1.8.3.1 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 2a00:1450:400c:c09::241 Subject: [Qemu-devel] [PATCH v2 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Cave-Ayland , Artyom Tarasenko , Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In OpenSPARC T1+ TWINX ASIs in store instructions are aliased with Block Initializing Store ASIs. "UltraSPARC T1 Supplement Draft D2.1, 14 May 2007" describes them in the chapter "5.9 Block Initializing Store ASIs" Integer stores of all sizes are allowed with these ASIs. Signed-off-by: Artyom Tarasenko --- target/sparc/translate.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 53c327d..e929169 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -2321,8 +2321,19 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, case GET_ASI_EXCP: break; case GET_ASI_DTWINX: /* Reserved for stda. */ +#ifndef TARGET_SPARC64 gen_exception(dc, TT_ILL_INSN); break; +#else + if (!(dc->def->features & CPU_FEATURE_HYPV)) { + /* Pre OpenSPARC CPUs don't have these */ + gen_exception(dc, TT_ILL_INSN); + return; + } + /* in OpenSPARC T1+ CPUs TWINX ASIs in store instructions + * are ST_BLKINIT_ ASIs */ + /* fall through */ +#endif case GET_ASI_DIRECT: gen_address_mask(dc, addr); tcg_gen_qemu_st_tl(src, addr, da.mem_idx, da.memop);