From patchwork Mon Nov 3 18:47:45 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Maciej W. Rozycki" X-Patchwork-Id: 406330 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id C880414009E for ; Tue, 4 Nov 2014 05:48:27 +1100 (AEDT) Received: from localhost ([::1]:36791 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlMfy-0004Rv-1J for incoming@patchwork.ozlabs.org; Mon, 03 Nov 2014 13:48:26 -0500 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55985) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlMfY-0003vU-7k for qemu-devel@nongnu.org; Mon, 03 Nov 2014 13:48:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlMfR-0000Fd-5Q for qemu-devel@nongnu.org; Mon, 03 Nov 2014 13:48:00 -0500 Received: from relay1.mentorg.com ([192.94.38.131]:49948) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlMfR-0000FX-0L for qemu-devel@nongnu.org; Mon, 03 Nov 2014 13:47:53 -0500 Received: from nat-ies.mentorg.com ([192.94.31.2] helo=SVR-IES-FEM-01.mgc.mentorg.com) by relay1.mentorg.com with esmtp id 1XlMfO-0004L1-S8 from Maciej_Rozycki@mentor.com ; Mon, 03 Nov 2014 10:47:51 -0800 Received: from localhost (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server (TLS) id 14.3.181.6; Mon, 3 Nov 2014 18:47:49 +0000 Date: Mon, 3 Nov 2014 18:47:45 +0000 From: "Maciej W. Rozycki" To: Message-ID: User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Windows NT kernel [generic] [fuzzy] X-Received-From: 192.94.38.131 Cc: Leon Alrae , Aurelien Jarno Subject: [Qemu-devel] [PATCH] mips/gdbstub: Correct the handling of register #72 on writes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Fix an off-by-one error in `mips_cpu_gdb_write_register' for register #72 that is handled further down in that function rather than here, matching how `mips_cpu_gdb_read_register' handles it. This register slot is a fake anyway, there's nothing in hardware that corresponds to it. Signed-off-by: Maciej W. Rozycki Reviewed-by: Leon Alrae --- I have a further change down the queue to clean up `mips_cpu_gdb_read_register' and `mips_cpu_gdb_write_register' and make them more consistent with respect to each other as far as the handling of FP registers is concerned. For now please apply this obvious change. Thanks. Maciej qemu-mips-fpreg72.diff Index: qemu-git-trunk/target-mips/gdbstub.c =================================================================== --- qemu-git-trunk.orig/target-mips/gdbstub.c 2013-07-29 11:23:07.048742983 +0100 +++ qemu-git-trunk/target-mips/gdbstub.c 2014-10-27 04:17:19.159003270 +0000 @@ -97,7 +97,7 @@ int mips_cpu_gdb_write_register(CPUState return sizeof(target_ulong); } if (env->CP0_Config1 & (1 << CP0C1_FP) - && n >= 38 && n < 73) { + && n >= 38 && n < 72) { if (n < 70) { if (env->CP0_Status & (1 << CP0St_FR)) { env->active_fpu.fpr[n - 38].d = tmp;