@@ -215,7 +215,8 @@ mips_mipssim_init (ram_addr_t ram_size,
/* A single 16450 sits at offset 0x3f8. It is attached to
MIPS CPU INT2, which is interrupt 4. */
if (serial_hds[0])
- serial_init(0x3f8, env->irq[4], 115200, serial_hds[0]);
+ serial_init(0x3f8, env->irq[4], 115200, serial_hds[0],
+ get_system_io());
if (nd_table[0].used)
/* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */
@@ -15,7 +15,7 @@
/* serial.c */
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
- CharDriverState *chr);
+ CharDriverState *chr, MemoryRegion *system_io);
SerialState *serial_mm_init(MemoryRegion *address_space,
target_phys_addr_t base, int it_shift,
qemu_irq irq, int baudbase,
@@ -28,6 +28,7 @@
#include "pc.h"
#include "qemu-timer.h"
#include "sysemu.h"
+#include "exec-memory.h"
//#define DEBUG_SERIAL
@@ -810,7 +811,7 @@ static const VMStateDescription vmstate_isa_serial = {
};
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
- CharDriverState *chr)
+ CharDriverState *chr, MemoryRegion *system_io)
{
SerialState *s;
@@ -823,8 +824,9 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase,
vmstate_register(NULL, base, &vmstate_serial, s);
- register_ioport_write(base, 8, 1, serial_ioport_write, s);
- register_ioport_read(base, 8, 1, serial_ioport_read, s);
+ memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8);
+ memory_region_add_subregion(system_io, base, &s->io);
+
return s;
}
This patch replaces all register_ioport* with a MemoryRegion. It permits to use the new Memory stuff like listener. For more flexibility, the IO address space is passed as an argument. Signed-off-by: Julien Grall <julien.grall@citrix.com> --- hw/mips_mipssim.c | 3 ++- hw/pc.h | 2 +- hw/serial.c | 8 +++++--- 3 files changed, 8 insertions(+), 5 deletions(-)