From patchwork Fri Jun 5 12:03:26 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jan Beulich X-Patchwork-Id: 481183 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id D8CCD14027F for ; Fri, 5 Jun 2015 22:07:27 +1000 (AEST) Received: from localhost ([::1]:46876 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0qPG-0007Qs-01 for incoming@patchwork.ozlabs.org; Fri, 05 Jun 2015 08:07:26 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40746) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0qLV-00018Y-Fe for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:03:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0qLP-0004uy-S4 for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:03:33 -0400 Received: from mail.emea.novell.com ([130.57.118.101]:55425) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0qLP-0004ui-G9 for qemu-devel@nongnu.org; Fri, 05 Jun 2015 08:03:27 -0400 Received: from EMEA1-MTA by mail.emea.novell.com with Novell_GroupWise; Fri, 05 Jun 2015 13:03:26 +0100 Message-Id: <5571AC2E020000780008156B@mail.emea.novell.com> X-Mailer: Novell GroupWise Internet Agent 14.0.1 Date: Fri, 05 Jun 2015 13:03:26 +0100 From: "Jan Beulich" To: References: <5571AA3B020000780008152E@mail.emea.novell.com> In-Reply-To: <5571AA3B020000780008152E@mail.emea.novell.com> Mime-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x X-Received-From: 130.57.118.101 Cc: xen-devel , Stefano Stabellini Subject: [Qemu-devel] [PATCH 4/6] xen/pass-through: correctly deal with RW1C bits X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Introduce yet another mask for them, so that the generic routine can handle them, at once rendering xen_pt_pmcsr_reg_write() superfluous. Signed-off-by: Jan Beulich xen/pass-through: correctly deal with RW1C bits Introduce yet another mask for them, so that the generic routine can handle them, at once rendering xen_pt_pmcsr_reg_write() superfluous. Signed-off-by: Jan Beulich --- a/qemu/upstream/hw/xen/xen_pt.h +++ b/qemu/upstream/hw/xen/xen_pt.h @@ -105,6 +105,8 @@ struct XenPTRegInfo { uint32_t res_mask; /* reg read only field mask (ON:RO/ROS, OFF:other) */ uint32_t ro_mask; + /* reg read/write-1-clear field mask (ON:RW1C/RW1CS, OFF:other) */ + uint32_t rw1c_mask; /* reg emulate field mask (ON:emu, OFF:passthrough) */ uint32_t emu_mask; xen_pt_conf_reg_init init; --- a/qemu/upstream/hw/xen/xen_pt_config_init.c +++ b/qemu/upstream/hw/xen/xen_pt_config_init.c @@ -176,7 +176,8 @@ static int xen_pt_byte_reg_write(XenPCIP cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ - *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); + *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask, + throughable_mask); return 0; } @@ -193,7 +194,8 @@ static int xen_pt_word_reg_write(XenPCIP cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ - *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); + *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask, + throughable_mask); return 0; } @@ -210,7 +212,8 @@ static int xen_pt_long_reg_write(XenPCIP cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ - *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); + *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask, + throughable_mask); return 0; } @@ -611,6 +614,7 @@ static XenPTRegInfo xen_pt_emu_reg_heade .init_val = 0x0000, .res_mask = 0x0007, .ro_mask = 0x06F8, + .rw1c_mask = 0xF900, .emu_mask = 0x0010, .init = xen_pt_status_reg_init, .u.w.read = xen_pt_word_reg_read, @@ -910,6 +914,7 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[ .size = 2, .res_mask = 0xFFC0, .ro_mask = 0x0030, + .rw1c_mask = 0x000F, .init = xen_pt_common_reg_init, .u.w.read = xen_pt_word_reg_read, .u.w.write = xen_pt_word_reg_write, @@ -930,6 +935,7 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[ .offset = PCI_EXP_LNKSTA, .size = 2, .ro_mask = 0x3FFF, + .rw1c_mask = 0xC000, .init = xen_pt_common_reg_init, .u.w.read = xen_pt_word_reg_read, .u.w.write = xen_pt_word_reg_write, @@ -966,26 +972,6 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[ * Power Management Capability */ -/* write Power Management Control/Status register */ -static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState *s, - XenPTReg *cfg_entry, uint16_t *val, - uint16_t dev_value, uint16_t valid_mask) -{ - XenPTRegInfo *reg = cfg_entry->reg; - uint16_t writable_mask = 0; - uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask); - - /* modify emulate register */ - writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); - - /* create value for writing to I/O device register */ - *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~PCI_PM_CTRL_PME_STATUS, - throughable_mask); - - return 0; -} - /* Power Management Capability reg static information table */ static XenPTRegInfo xen_pt_emu_reg_pm[] = { /* Next Pointer reg */ @@ -1016,11 +1002,12 @@ static XenPTRegInfo xen_pt_emu_reg_pm[] .size = 2, .init_val = 0x0008, .res_mask = 0x00F0, - .ro_mask = 0xE10C, + .ro_mask = 0x610C, + .rw1c_mask = 0x8000, .emu_mask = 0x810B, .init = xen_pt_common_reg_init, .u.w.read = xen_pt_word_reg_read, - .u.w.write = xen_pt_pmcsr_reg_write, + .u.w.write = xen_pt_word_reg_write, }, { .size = 0, --- a/qemu/upstream/hw/xen/xen_pt.h +++ b/qemu/upstream/hw/xen/xen_pt.h @@ -105,6 +105,8 @@ struct XenPTRegInfo { uint32_t res_mask; /* reg read only field mask (ON:RO/ROS, OFF:other) */ uint32_t ro_mask; + /* reg read/write-1-clear field mask (ON:RW1C/RW1CS, OFF:other) */ + uint32_t rw1c_mask; /* reg emulate field mask (ON:emu, OFF:passthrough) */ uint32_t emu_mask; xen_pt_conf_reg_init init; --- a/qemu/upstream/hw/xen/xen_pt_config_init.c +++ b/qemu/upstream/hw/xen/xen_pt_config_init.c @@ -176,7 +176,8 @@ static int xen_pt_byte_reg_write(XenPCIP cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ - *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); + *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask, + throughable_mask); return 0; } @@ -193,7 +194,8 @@ static int xen_pt_word_reg_write(XenPCIP cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ - *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); + *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask, + throughable_mask); return 0; } @@ -210,7 +212,8 @@ static int xen_pt_long_reg_write(XenPCIP cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ - *val = XEN_PT_MERGE_VALUE(*val, dev_value, throughable_mask); + *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~reg->rw1c_mask, + throughable_mask); return 0; } @@ -611,6 +614,7 @@ static XenPTRegInfo xen_pt_emu_reg_heade .init_val = 0x0000, .res_mask = 0x0007, .ro_mask = 0x06F8, + .rw1c_mask = 0xF900, .emu_mask = 0x0010, .init = xen_pt_status_reg_init, .u.w.read = xen_pt_word_reg_read, @@ -910,6 +914,7 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[ .size = 2, .res_mask = 0xFFC0, .ro_mask = 0x0030, + .rw1c_mask = 0x000F, .init = xen_pt_common_reg_init, .u.w.read = xen_pt_word_reg_read, .u.w.write = xen_pt_word_reg_write, @@ -930,6 +935,7 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[ .offset = PCI_EXP_LNKSTA, .size = 2, .ro_mask = 0x3FFF, + .rw1c_mask = 0xC000, .init = xen_pt_common_reg_init, .u.w.read = xen_pt_word_reg_read, .u.w.write = xen_pt_word_reg_write, @@ -966,26 +972,6 @@ static XenPTRegInfo xen_pt_emu_reg_pcie[ * Power Management Capability */ -/* write Power Management Control/Status register */ -static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState *s, - XenPTReg *cfg_entry, uint16_t *val, - uint16_t dev_value, uint16_t valid_mask) -{ - XenPTRegInfo *reg = cfg_entry->reg; - uint16_t writable_mask = 0; - uint16_t throughable_mask = get_throughable_mask(s, reg, valid_mask); - - /* modify emulate register */ - writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = XEN_PT_MERGE_VALUE(*val, cfg_entry->data, writable_mask); - - /* create value for writing to I/O device register */ - *val = XEN_PT_MERGE_VALUE(*val, dev_value & ~PCI_PM_CTRL_PME_STATUS, - throughable_mask); - - return 0; -} - /* Power Management Capability reg static information table */ static XenPTRegInfo xen_pt_emu_reg_pm[] = { /* Next Pointer reg */ @@ -1016,11 +1002,12 @@ static XenPTRegInfo xen_pt_emu_reg_pm[] .size = 2, .init_val = 0x0008, .res_mask = 0x00F0, - .ro_mask = 0xE10C, + .ro_mask = 0x610C, + .rw1c_mask = 0x8000, .emu_mask = 0x810B, .init = xen_pt_common_reg_init, .u.w.read = xen_pt_word_reg_read, - .u.w.write = xen_pt_pmcsr_reg_write, + .u.w.write = xen_pt_word_reg_write, }, { .size = 0,