@@ -63,6 +63,8 @@ typedef struct PIIX4PMState {
PMSMBus smb;
uint32_t smb_io_base;
+ MemoryRegion smb_io;
+
qemu_irq irq;
qemu_irq smi_irq;
int kvm_enabled;
@@ -383,6 +385,16 @@ static void piix4_pm_machine_ready(Notifier *n, void *opaque)
}
+static const MemoryRegionOps smb_io_ops = {
+ .read = smb_ioport_readb,
+ .write = smb_ioport_writeb,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
static int piix4_pm_initfn(PCIDevice *dev)
{
PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
@@ -410,8 +422,10 @@ static int piix4_pm_initfn(PCIDevice *dev)
pci_conf[0x90] = s->smb_io_base | 1;
pci_conf[0x91] = s->smb_io_base >> 8;
pci_conf[0xd2] = 0x09;
- register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
- register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
+
+ memory_region_init_io(&s->smb_io, &smb_io_ops, &s->smb, "piix4-smb", 64);
+ memory_region_add_subregion(pci_address_space_io(dev), s->smb_io_base,
+ &s->smb_io);
acpi_pm_tmr_init(&s->ar, pm_tmr_timer);
acpi_gpe_init(&s->ar, GPE_LEN);
@@ -94,7 +94,8 @@ static void smb_transaction(PMSMBus *s)
s->smb_stat |= 0x04;
}
-void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+void smb_ioport_writeb(void *opaque, target_phys_addr_t addr, uint64_t val,
+ unsigned size)
{
PMSMBus *s = opaque;
addr &= 0x3f;
@@ -131,10 +132,10 @@ void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
}
}
-uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
+uint64_t smb_ioport_readb(void *opaque, target_phys_addr_t addr, unsigned size)
{
PMSMBus *s = opaque;
- uint32_t val;
+ uint64_t val;
addr &= 0x3f;
switch(addr) {
@@ -15,7 +15,9 @@ typedef struct PMSMBus {
} PMSMBus;
void pm_smbus_init(DeviceState *parent, PMSMBus *smb);
-void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val);
-uint32_t smb_ioport_readb(void *opaque, uint32_t addr);
+void smb_ioport_writeb(void *opaque, target_phys_addr_t addr, uint64_t val,
+ unsigned size);
+uint64_t smb_ioport_readb(void *opaque, target_phys_addr_t addr,
+ unsigned size);
#endif /* !PM_SMBUS_H */
@@ -163,6 +163,7 @@ typedef struct VT686PMState {
APMState apm;
PMSMBus smb;
uint32_t smb_io_base;
+ MemoryRegion smb_io;
} VT686PMState;
typedef struct VT686AC97State {
@@ -405,6 +406,16 @@ static TypeInfo via_mc97_info = {
.class_init = via_mc97_class_init,
};
+static const MemoryRegionOps smb_io_ops = {
+ .read = smb_ioport_readb,
+ .write = smb_ioport_writeb,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
/* vt82c686 pm init */
static int vt82c686b_pm_initfn(PCIDevice *dev)
{
@@ -424,8 +435,11 @@ static int vt82c686b_pm_initfn(PCIDevice *dev)
pci_conf[0x90] = s->smb_io_base | 1;
pci_conf[0x91] = s->smb_io_base >> 8;
pci_conf[0xd2] = 0x90;
- register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb);
- register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb);
+
+ memory_region_init_io(&s->smb_io, &smb_io_ops, &s->smb, "vt82c686b-smb",
+ 0xf);
+ memory_region_add_subregion(pci_address_space_io(dev), s->smb_io_base,
+ &s->smb_io);
apm_init(dev, &s->apm, NULL, s);
This patch fix smb_ioport_* to be compliant with read/write memory callback. Moreover it replaces all register_ioport* which use theses functions by the new Memory API. Signed-off-by: Julien Grall <julien.grall@citrix.com> --- hw/acpi_piix4.c | 18 ++++++++++++++++-- hw/pm_smbus.c | 7 ++++--- hw/pm_smbus.h | 6 ++++-- hw/vt82c686.c | 18 ++++++++++++++++-- 4 files changed, 40 insertions(+), 9 deletions(-)