@@ -94,6 +94,7 @@ uint8_t qpci_find_capability(QPCIDevice *dev, uint8_t id, uint8_t start_addr);
void qpci_msix_enable(QPCIDevice *dev);
void qpci_msix_disable(QPCIDevice *dev);
bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry);
+bool qpci_msix_test_clear_pending(QPCIDevice *dev, uint16_t entry);
bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry);
uint16_t qpci_msix_table_size(QPCIDevice *dev);
@@ -260,6 +260,22 @@ static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr,
static void msix_pba_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
+ PCIDevice *dev = opaque;
+ unsigned vector_start = addr * 8;
+ unsigned vector_end = MIN(addr + size * 8, dev->msix_entries_nr);
+ unsigned i;
+
+ for (i = vector_start; i < vector_end; i++) {
+ if ((val >> i) & 1) {
+ if (!msix_is_pending(dev, i)) {
+ msix_notify(dev, i);
+ }
+ } else {
+ if (msix_is_pending(dev, i)) {
+ msix_clr_pending(dev, i);
+ }
+ }
+ }
}
static const MemoryRegionOps msix_pba_mmio_ops = {
@@ -343,11 +343,26 @@ bool qpci_msix_pending(QPCIDevice *dev, uint16_t entry)
g_assert(dev->msix_enabled);
pba_entry = qpci_io_readl(dev, dev->msix_pba_bar, dev->msix_pba_off + off);
- qpci_io_writel(dev, dev->msix_pba_bar, dev->msix_pba_off + off,
- pba_entry & ~(1 << bit_n));
- return (pba_entry & (1 << bit_n)) != 0;
+ return (pba_entry & (1 << bit_n));
}
+bool qpci_msix_test_clear_pending(QPCIDevice *dev, uint16_t entry)
+{
+ uint32_t pba_entry;
+ uint8_t bit_n = entry % 32;
+ uint64_t off = (entry / 32) * PCI_MSIX_ENTRY_SIZE / 4;
+
+ g_assert(dev->msix_enabled);
+ pba_entry = qpci_io_readl(dev, dev->msix_pba_bar, dev->msix_pba_off + off);
+ if (pba_entry & (1 << bit_n)) {
+ qpci_io_writel(dev, dev->msix_pba_bar, dev->msix_pba_off + off,
+ pba_entry & ~(1 << bit_n));
+ return true;
+ }
+ return false;
+}
+
+
bool qpci_msix_masked(QPCIDevice *dev, uint16_t entry)
{
uint8_t addr;
Implement PBA write 1 to trigger and 0 to clear. This is used by qtests which mask the MSI irq and so the bits remain pending and expect to be cleared with stores. Some devices like e1000e seem to have MSIX PBA pending tied to some device state level, as such they call msix_clr_pending() directly, and clearing pending via a store to PBA causes this to go out of synch. So the qpci_msix_pending() function is changed to avoid clearing, and a new test-and-clear function is added for tests that would like to clear. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- tests/qtest/libqos/pci.h | 1 + hw/pci/msix.c | 16 ++++++++++++++++ tests/qtest/libqos/pci.c | 21 ++++++++++++++++++--- 3 files changed, 35 insertions(+), 3 deletions(-)