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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-1f8393e8e53sm11363875ad.16.2024.06.12.01.15.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Jun 2024 01:15:33 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Richard Henderson , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Eduardo Habkost , Marcel Apfelbaum , =?utf-8?q?Philippe_Mathieu-D?= =?utf-8?q?aud=C3=A9?= , Yanan Wang , Peter Xu , David Hildenbrand , Peter Maydell , Michael Rolnik , "Edgar E. Iglesias" , Song Gao , Laurent Vivier , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo , Stafford Horne , Nicholas Piggin , Yoshinori Sato , Ilya Leoshkevich , Thomas Huth , Mark Cave-Ayland , Artyom Tarasenko , Bastian Koppelmann , Max Filippov , qemu-arm@nongnu.org (open list:ARM TCG CPUs), qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs), qemu-s390x@nongnu.org (open list:S390 TCG CPUs), Jim Shu Subject: [RFC PATCH 10/16] target/riscv: Add WID to MemTxAttrs of CPU memory transactions Date: Wed, 12 Jun 2024 16:14:10 +0800 Message-Id: <20240612081416.29704-11-jim.shu@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240612081416.29704-1-jim.shu@sifive.com> References: <20240612081416.29704-1-jim.shu@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=jim.shu@sifive.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org When a RISC-V HART has WG extension, their memory transactions will contain WID. Support MemTxAttrs in RISC-V target and add WID inside if a HART has WG extension. Signed-off-by: Jim Shu --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 51 ++++++++++++++++++++++++++++++++++++--- 3 files changed, 50 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ff1c22c71c..55d980ff4b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2343,7 +2343,7 @@ static int64_t riscv_get_arch_id(CPUState *cs) #include "hw/core/sysemu-cpu-ops.h" static const struct SysemuCPUOps riscv_sysemu_ops = { - .get_phys_page_debug = riscv_cpu_get_phys_page_debug, + .get_phys_page_attrs_debug = riscv_cpu_get_phys_page_attrs_debug, .write_elf64_note = riscv_cpu_write_elf64_note, .write_elf32_note = riscv_cpu_write_elf32_note, .legacy_vmsd = &vmstate_riscv_cpu, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 43ab558111..588f5de7f7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -512,6 +512,7 @@ void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); bool riscv_cpu_vector_enabled(CPURISCVState *env); void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); +hwaddr riscv_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index ff20ab6ab8..afdccdd672 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -150,6 +150,34 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, } #ifndef CONFIG_USER_ONLY +static uint32_t riscv_cpu_wg_get_wid(CPURISCVState *env, int mode) +{ + CPUState *cs = env_cpu(env); + RISCVCPU *cpu = RISCV_CPU(cs); + bool virt = env->virt_enabled; + + if (mode == PRV_M) { + return cpu->cfg.mwid; + } else if (mode == PRV_S) { + if (!virt || !env->mwiddeleg) { + /* HS-mode, S-mode w/o RVH, or VS-mode but mwiddeleg = 0 */ + return env->mlwid; + } else { + /* VS-mode */ + return env->slwid; + } + } else if (mode == PRV_U) { + if (!riscv_has_ext(env, RVS) || !env->mwiddeleg) { + /* M/U mode CPU or mwiddeleg = 0 */ + return env->mlwid; + } else { + return env->slwid; + } + } + + return cpu->cfg.mwid; +} + void riscv_cpu_set_wg_mwid(CPURISCVState *env, uint32_t mwid) { CPUState *cs = env_cpu(env); @@ -1229,13 +1257,22 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address, env->two_stage_indirect_lookup = two_stage_indirect; } -hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr riscv_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, MemTxAttrs *attrs) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; hwaddr phys_addr; int prot; int mmu_idx = riscv_env_mmu_index(&cpu->env, false); + int mode = mmuidx_priv(mmu_idx); + uint32_t wid; + + if (riscv_cpu_cfg(env)->ext_smwg && env->wid_to_mem_attrs) { + wid = riscv_cpu_wg_get_wid(env, mode); + env->wid_to_mem_attrs(attrs, wid); + } else { + *attrs = MEMTXATTRS_UNSPECIFIED; + } if (get_physical_address(env, &phys_addr, &prot, addr, NULL, 0, mmu_idx, true, env->virt_enabled, true)) { @@ -1339,12 +1376,20 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, int mode = mmuidx_priv(mmu_idx); /* default TLB page size */ target_ulong tlb_size = TARGET_PAGE_SIZE; + uint32_t wid; + MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; env->guest_phys_fault_addr = 0; qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n", __func__, address, access_type, mmu_idx); + if (riscv_cpu_cfg(env)->ext_smwg && env->wid_to_mem_attrs) { + mode = mmuidx_priv(mmu_idx); + wid = riscv_cpu_wg_get_wid(env, mode); + env->wid_to_mem_attrs(&attrs, wid); + } + pmu_tlb_fill_incr_ctr(cpu, access_type); if (two_stage_lookup) { /* Two stage lookup */ @@ -1436,8 +1481,8 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } if (ret == TRANSLATE_SUCCESS) { - tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), - prot, access_type, mmu_idx, tlb_size); + tlb_set_page_with_attrs(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), + attrs, prot, access_type, mmu_idx, tlb_size); return true; } else if (probe) { return false;