@@ -17,6 +17,7 @@ Currently B-L475E-IOT01A machine's only supports the following devices:
- Cortex-M4F based STM32L4x5 SoC
- STM32L4x5 EXTI (Extended interrupts and events controller)
- STM32L4x5 SYSCFG (System configuration controller)
+- STM32L4x5 GPIOs (General-purpose I/Os)
Missing devices
"""""""""""""""
@@ -25,7 +26,6 @@ The B-L475E-IOT01A does *not* support the following devices:
- Reset and clock control (RCC)
- Serial ports (UART)
-- General-purpose I/Os (GPIO)
- Analog to Digital Converter (ADC)
- SPI controller
- Timer controller (TIMER)
@@ -16,3 +16,6 @@ config GPIO_PWR
config SIFIVE_GPIO
bool
+
+config STM32L4X5_GPIO
+ bool
@@ -9,6 +9,7 @@ system_ss.add(when: 'CONFIG_IMX', if_true: files('imx_gpio.c'))
system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_gpio.c'))
system_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('nrf51_gpio.c'))
system_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c'))
+system_ss.add(when: 'CONFIG_STM32L4X5_SOC', if_true: files('stm32l4x5_gpio.c'))
system_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c'))
system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c'))
system_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c'))
new file mode 100644
@@ -0,0 +1,520 @@
+/*
+ * STM32L4x5 GPIO (General Purpose Input/Ouput)
+ *
+ * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+/*
+ * The reference used is the STMicroElectronics RM0351 Reference manual
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "hw/gpio/stm32l4x5_gpio.h"
+#include "hw/irq.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+#define GPIO_MODER 0x00
+#define GPIO_OTYPER 0x04
+#define GPIO_OSPEEDR 0x08
+#define GPIO_PUPDR 0x0C
+#define GPIO_IDR 0x10
+#define GPIO_ODR 0x14
+#define GPIO_BSRR 0x18
+#define GPIO_LCKR 0x1C
+#define GPIO_AFRL 0x20
+#define GPIO_AFRH 0x24
+#define GPIO_BRR 0x28
+#define GPIO_ASCR 0x2C
+/*
+ * DISCONNECTED_PINS isn't actually a GPIO register.
+ * It exists to ensure that :
+ * - push-pull output pins can't be set externally
+ * - open-drain output pins can only be externally set to 0
+ *
+ * This field is accessed for test purposes.
+ */
+#define GPIO_DISCONNECTED_PINS 0x30
+
+/* 0b11111111_11111111_00000000_00000000 */
+#define RESERVED_BITS_MASK 0xFFFF0000
+
+static void update_gpio_idr(Stm32l4x5GpioState *s);
+
+static void stm32l4x5_gpio_reset_hold(Object *obj)
+{
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
+ Stm32l4x5GpioClass *sc = STM32L4X5_GPIO_GET_CLASS(obj);
+
+ s->moder = sc->moder_reset;
+ s->otyper = 0x00000000;
+ s->ospeedr = sc->ospeedr_reset;
+ s->pupdr = sc->pupdr_reset;
+ s->idr = 0x00000000;
+ s->odr = 0x00000000;
+ s->lckr = 0x00000000;
+ s->afrl = 0x00000000;
+ s->afrh = 0x00000000;
+ s->ascr = 0x00000000;
+
+ s->disconnected_pins = 0xFFFF;
+ s->pins_connected_high = 0x0000;
+ update_gpio_idr(s);
+}
+
+static void stm32l4x5_gpio_set(void *opaque, int line, int level)
+{
+ Stm32l4x5GpioState *s = opaque;
+ /*
+ * The pin isn't set if line is configured in output mode
+ * except if level is 0 and the output is open-drain.
+ * This way there will be no short-circuit prone situations.
+ */
+ if ((extract32(s->moder, 2 * line, 2) == 1) &&
+ !((extract32(s->otyper, line, 1) == 1) &&
+ (level == 0))) {
+ qemu_log_mask(LOG_GUEST_ERROR, "Line %d can't be driven externally\n",
+ line);
+ return;
+ }
+
+ s->disconnected_pins &= ~(1 << line);
+ if (level) {
+ s->pins_connected_high |= (1 << line);
+ } else {
+ s->pins_connected_high &= ~(1 << line);
+ }
+ trace_stm32l4x5_gpio_pins(s->disconnected_pins,
+ s->pins_connected_high);
+ update_gpio_idr(s);
+}
+
+
+static void update_gpio_idr(Stm32l4x5GpioState *s)
+{
+ uint32_t new_idr_mask = 0;
+ uint32_t new_idr = s->odr;
+
+ for (int i = 0; i < 16; i++) {
+ /* output mode */
+ if (extract32(s->moder, 2 * i, 2) == 1) {
+ if (extract32(s->otyper, i, 1) == 0) {
+ /* push-pull */
+ new_idr_mask |= (1 << i);
+ } else if (!(s->odr & (1 << i))) {
+ /* open-drain ODR 0 */
+ new_idr_mask |= (1 << i);
+ } else if ((s->disconnected_pins & (1 << i)) &&
+ (extract32(s->pupdr, 2 * i, 2) == 1)) {
+ /* open-drain pull-up ODR 1 with floating pin */
+ new_idr_mask |= (1 << i);
+ } else if ((s->disconnected_pins & (1 << i)) &&
+ (extract32(s->pupdr, 2 * i, 2) == 2)) {
+ /* open-drain pull-down ODR 1 with floating pin */
+ new_idr_mask |= (1 << i);
+ new_idr &= ~(1 << i);
+ } else if (!(s->pins_connected_high & (1 << i))) {
+ /* open-drain ODR 1 with pin connected low */
+ new_idr_mask |= (1 << i);
+ new_idr &= ~(1 << i);
+ } else {
+ /* open-drain ODR 1 with pin connected high */
+ assert(false);
+ }
+ /* input or analog mode with connected pin */
+ } else if (!(s->disconnected_pins & (1 << i))) {
+ if (s->pins_connected_high & (1 << i)) {
+ /* pin high */
+ new_idr_mask |= (1 << i);
+ new_idr |= (1 << i);
+ } else {
+ /* pin low */
+ new_idr_mask |= (1 << i);
+ new_idr &= ~(1 << i);
+ }
+ /* input or analog mode with disconnected pin */
+ } else {
+ if (extract32(s->pupdr, 2 * i, 2) == 1) {
+ /* pull-up */
+ new_idr_mask |= (1 << i);
+ new_idr |= (1 << i);
+ } else if (extract32(s->pupdr, 2 * i, 2) == 2) {
+ /* pull-down */
+ new_idr_mask |= (1 << i);
+ new_idr &= ~(1 << i);
+ }
+ }
+ }
+
+ uint32_t old_idr = s->idr;
+ s->idr = (old_idr & ~new_idr_mask) | (new_idr & new_idr_mask);
+ trace_stm32l4x5_gpio_update_idr(old_idr, s->idr);
+
+ for (int i = 0; i < 16; i++) {
+ if (new_idr_mask & (1 << i)) {
+ if ((new_idr & (1 << i)) > (old_idr & (1 << i))) {
+ qemu_irq_raise(s->pin[i]);
+ } else if ((new_idr & (1 << i)) < (old_idr & (1 << i))) {
+ qemu_irq_lower(s->pin[i]);
+ }
+ }
+ }
+}
+
+/*
+ * Return pins both configured in output mode
+ * and externally driven (except pins in open-drain
+ * mode externally set to 0).
+ */
+static uint32_t get_gpio_pins_to_disconnect(Stm32l4x5GpioState *s)
+{
+ uint32_t pins_to_disconnect = 0;
+ for (int i = 0; i < 16; i++) {
+ /* for each connected pin in output mode */
+ if ((~s->disconnected_pins & (1 << i)) &
+ (extract32(s->moder, 2 * i, 2) == 1)) {
+ /* if either push-pull or high level */
+ if ((extract32(s->otyper, i, 1) == 0) ||
+ (extract16(s->pins_connected_high, i, 1)) == 1) {
+ pins_to_disconnect |= (1 << i);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "Line %d can't be driven externally\n",
+ i);
+ }
+ }
+ }
+ return pins_to_disconnect;
+}
+
+/*
+ * Set field `disconnected_pins` and call `update_gpio_idr()`
+ */
+static void disconnect_gpio_pins(Stm32l4x5GpioState *s, uint16_t lines)
+{
+ s->disconnected_pins |= lines;
+ trace_stm32l4x5_gpio_pins(s->disconnected_pins,
+ s->pins_connected_high);
+ update_gpio_idr(s);
+}
+
+static void stm32l4x5_gpio_write(void *opaque, hwaddr addr,
+ uint64_t val64, unsigned int size)
+{
+ Stm32l4x5GpioState *s = opaque;
+
+ uint32_t value = val64;
+ trace_stm32l4x5_gpio_write(addr, val64);
+
+ switch (addr) {
+ case GPIO_MODER:
+ s->moder = value;
+ disconnect_gpio_pins(s, get_gpio_pins_to_disconnect(s));
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Alternate function mode isn't supported\n\
+ Setting alternate function mode sets analog mode\n",
+ __func__);
+ return;
+ case GPIO_OTYPER:
+ s->otyper = value & ~RESERVED_BITS_MASK;
+ disconnect_gpio_pins(s, get_gpio_pins_to_disconnect(s));
+ return;
+ case GPIO_OSPEEDR:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Changing the I/O output speed isn't supported\n",
+ __func__);
+ s->ospeedr = value;
+ return;
+ case GPIO_PUPDR:
+ s->pupdr = value;
+ update_gpio_idr(s);
+ return;
+ case GPIO_IDR:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: GPIO->IDR is read-only\n",
+ __func__);
+ return;
+ case GPIO_ODR:
+ s->odr = value & ~RESERVED_BITS_MASK;
+ update_gpio_idr(s);
+ return;
+ case GPIO_BSRR: {
+ uint32_t bits_to_reset = (value & RESERVED_BITS_MASK) >> 16;
+ uint32_t bits_to_set = value & ~RESERVED_BITS_MASK;
+ /* If both BSx and BRx are set, BSx has priority.*/
+ s->odr &= ~bits_to_reset;
+ s->odr |= bits_to_set;
+ update_gpio_idr(s);
+ return;
+ }
+ case GPIO_LCKR:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Locking port bits configuration isn't supported\n",
+ __func__);
+ s->lckr = value & ~RESERVED_BITS_MASK;
+ return;
+ case GPIO_AFRL:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Alternate functions aren't supported\n",
+ __func__);
+ s->afrl = value;
+ return;
+ case GPIO_AFRH:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: Alternate functions aren't supported\n",
+ __func__);
+ s->afrh = value;
+ return;
+ case GPIO_BRR: {
+ uint32_t bits_to_reset = value & ~RESERVED_BITS_MASK;
+ s->odr &= ~bits_to_reset;
+ update_gpio_idr(s);
+ return;
+ }
+ case GPIO_ASCR:
+ qemu_log_mask(LOG_UNIMP,
+ "%s: ADC function isn't supported\n",
+ __func__);
+ s->ascr = value & ~RESERVED_BITS_MASK;
+ return;
+ /* a tweak to enable the qtest checking disconnected pins */
+ case GPIO_DISCONNECTED_PINS:
+ disconnect_gpio_pins(s, value);
+ return;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
+ }
+}
+
+static uint64_t stm32l4x5_gpio_read(void *opaque, hwaddr addr,
+ unsigned int size)
+{
+ Stm32l4x5GpioState *s = opaque;
+
+ trace_stm32l4x5_gpio_read(addr);
+
+ switch (addr) {
+ case GPIO_MODER:
+ return s->moder;
+ case GPIO_OTYPER:
+ return s->otyper;
+ case GPIO_OSPEEDR:
+ return s->ospeedr;
+ case GPIO_PUPDR:
+ return s->pupdr;
+ case GPIO_IDR:
+ return s->idr;
+ case GPIO_ODR:
+ return s->odr;
+ case GPIO_BSRR:
+ return 0;
+ case GPIO_LCKR:
+ return s->lckr;
+ case GPIO_AFRL:
+ return s->afrl;
+ case GPIO_AFRH:
+ return s->afrh;
+ case GPIO_BRR:
+ return 0;
+ case GPIO_ASCR:
+ return s->ascr;
+ /* a tweak to enable the qtest checking disconnected pins */
+ case GPIO_DISCONNECTED_PINS:
+ return s->disconnected_pins;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
+ return 0;
+ }
+}
+
+static const MemoryRegionOps stm32l4x5_gpio_ops = {
+ .read = stm32l4x5_gpio_read,
+ .write = stm32l4x5_gpio_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ .unaligned = false,
+ },
+};
+
+static void stm32l4x5_gpio_init(Object *obj)
+{
+ Stm32l4x5GpioState *s = STM32L4X5_GPIO(obj);
+ int i;
+
+ for (i = 0; i < GPIO_NUM_PINS; i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->pin[i]);
+ }
+
+ memory_region_init_io(&s->mmio, obj, &stm32l4x5_gpio_ops, s,
+ TYPE_STM32L4X5_GPIO, 0x400);
+
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
+
+ qdev_init_gpio_out(DEVICE(obj), s->pin, GPIO_NUM_PINS);
+ qdev_init_gpio_in(DEVICE(obj), stm32l4x5_gpio_set, GPIO_NUM_PINS);
+}
+
+static const VMStateDescription vmstate_stm32l4x5_gpio = {
+ .name = TYPE_STM32L4X5_GPIO,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]){
+ VMSTATE_UINT32(moder, Stm32l4x5GpioState),
+ VMSTATE_UINT32(otyper, Stm32l4x5GpioState),
+ VMSTATE_UINT32(ospeedr, Stm32l4x5GpioState),
+ VMSTATE_UINT32(pupdr, Stm32l4x5GpioState),
+ VMSTATE_UINT32(idr, Stm32l4x5GpioState),
+ VMSTATE_UINT32(odr, Stm32l4x5GpioState),
+ VMSTATE_UINT32(lckr, Stm32l4x5GpioState),
+ VMSTATE_UINT32(afrl, Stm32l4x5GpioState),
+ VMSTATE_UINT32(afrh, Stm32l4x5GpioState),
+ VMSTATE_UINT32(ascr, Stm32l4x5GpioState),
+ VMSTATE_UINT16(disconnected_pins, Stm32l4x5GpioState),
+ VMSTATE_UINT16(pins_connected_high, Stm32l4x5GpioState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void stm32l4x5_gpio_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+ dc->vmsd = &vmstate_stm32l4x5_gpio;
+ rc->phases.hold = stm32l4x5_gpio_reset_hold;
+}
+
+static void stm32l4x5_gpio_a_class_init(ObjectClass *klass, void *data)
+{
+ Stm32l4x5GpioClass *sc = STM32L4X5_GPIO_CLASS(klass);
+
+ sc->moder_reset = 0xABFFFFFF;
+ sc->ospeedr_reset = 0x0C000000;
+ sc->pupdr_reset = 0x64000000;
+}
+
+static void stm32l4x5_gpio_b_class_init(ObjectClass *klass, void *data)
+{
+ Stm32l4x5GpioClass *sc = STM32L4X5_GPIO_CLASS(klass);
+
+ sc->moder_reset = 0xFFFFFEBF;
+ sc->ospeedr_reset = 0x00000000;
+ sc->pupdr_reset = 0x00000100;
+}
+
+static void stm32l4x5_gpio_c_class_init(ObjectClass *klass, void *data)
+{
+ Stm32l4x5GpioClass *sc = STM32L4X5_GPIO_CLASS(klass);
+
+ sc->moder_reset = 0xFFFFFFFF;
+ sc->ospeedr_reset = 0x00000000;
+ sc->pupdr_reset = 0x00000000;
+}
+
+static void stm32l4x5_gpio_d_class_init(ObjectClass *klass, void *data)
+{
+ Stm32l4x5GpioClass *sc = STM32L4X5_GPIO_CLASS(klass);
+
+ sc->moder_reset = 0xFFFFFFFF;
+ sc->ospeedr_reset = 0x00000000;
+ sc->pupdr_reset = 0x00000000;
+}
+
+static void stm32l4x5_gpio_e_class_init(ObjectClass *klass, void *data)
+{
+ Stm32l4x5GpioClass *sc = STM32L4X5_GPIO_CLASS(klass);
+
+ sc->moder_reset = 0xFFFFFFFF;
+ sc->ospeedr_reset = 0x00000000;
+ sc->pupdr_reset = 0x00000000;
+}
+
+static void stm32l4x5_gpio_f_class_init(ObjectClass *klass, void *data)
+{
+ Stm32l4x5GpioClass *sc = STM32L4X5_GPIO_CLASS(klass);
+
+ sc->moder_reset = 0xFFFFFFFF;
+ sc->ospeedr_reset = 0x00000000;
+ sc->pupdr_reset = 0x00000000;
+}
+
+static void stm32l4x5_gpio_g_class_init(ObjectClass *klass, void *data)
+{
+ Stm32l4x5GpioClass *sc = STM32L4X5_GPIO_CLASS(klass);
+
+ sc->moder_reset = 0xFFFFFFFF;
+ sc->ospeedr_reset = 0x00000000;
+ sc->pupdr_reset = 0x00000000;
+}
+
+static void stm32l4x5_gpio_h_class_init(ObjectClass *klass, void *data)
+{
+ Stm32l4x5GpioClass *sc = STM32L4X5_GPIO_CLASS(klass);
+
+ sc->moder_reset = 0x0000000F;
+ sc->ospeedr_reset = 0x00000000;
+ sc->pupdr_reset = 0x00000000;
+}
+
+static const TypeInfo stm32l4x5_gpio_types[] = {
+ {
+ .name = TYPE_STM32L4X5_GPIO,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Stm32l4x5GpioState),
+ .instance_init = stm32l4x5_gpio_init,
+ .class_size = sizeof(Stm32l4x5GpioClass),
+ .class_init = stm32l4x5_gpio_class_init,
+ .abstract = true,
+ }, {
+ .name = TYPE_STM32L4X5_GPIO_A,
+ .parent = TYPE_STM32L4X5_GPIO,
+ .class_init = stm32l4x5_gpio_a_class_init,
+ }, {
+ .name = TYPE_STM32L4X5_GPIO_B,
+ .parent = TYPE_STM32L4X5_GPIO,
+ .class_init = stm32l4x5_gpio_b_class_init,
+ }, {
+ .name = TYPE_STM32L4X5_GPIO_C,
+ .parent = TYPE_STM32L4X5_GPIO,
+ .class_init = stm32l4x5_gpio_c_class_init,
+ }, {
+ .name = TYPE_STM32L4X5_GPIO_D,
+ .parent = TYPE_STM32L4X5_GPIO,
+ .class_init = stm32l4x5_gpio_d_class_init,
+ }, {
+ .name = TYPE_STM32L4X5_GPIO_E,
+ .parent = TYPE_STM32L4X5_GPIO,
+ .class_init = stm32l4x5_gpio_e_class_init,
+ }, {
+ .name = TYPE_STM32L4X5_GPIO_F,
+ .parent = TYPE_STM32L4X5_GPIO,
+ .class_init = stm32l4x5_gpio_f_class_init,
+ }, {
+ .name = TYPE_STM32L4X5_GPIO_G,
+ .parent = TYPE_STM32L4X5_GPIO,
+ .class_init = stm32l4x5_gpio_g_class_init,
+ }, {
+ .name = TYPE_STM32L4X5_GPIO_H,
+ .parent = TYPE_STM32L4X5_GPIO,
+ .class_init = stm32l4x5_gpio_h_class_init,
+ },
+};
+
+DEFINE_TYPES(stm32l4x5_gpio_types)
@@ -31,3 +31,9 @@ sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 " val
# aspeed_gpio.c
aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " value 0x%" PRIx64
+
+# stm32l4x5_gpio.c
+stm32l4x5_gpio_read(uint64_t addr) "reg read: addr: 0x%" PRIx64 " "
+stm32l4x5_gpio_write(uint64_t addr, uint64_t data) "reg write: addr: 0x%" PRIx64 " val: 0x%" PRIx64 ""
+stm32l4x5_gpio_update_idr(uint32_t old_idr, uint32_t new_idr) "previous idr: 0x%x new idr: 0x%x"
+stm32l4x5_gpio_pins(uint16_t disconnected, uint16_t high) "disconnected pins: 0x%x levels: 0x%x"
new file mode 100644
@@ -0,0 +1,79 @@
+/*
+ * STM32L4x5 GPIO (General Purpose Input/Ouput)
+ *
+ * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
+ * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+/*
+ * The reference used is the STMicroElectronics RM0351 Reference manual
+ * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
+ * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html
+ */
+
+#ifndef HW_STM32L4X5_GPIO_H
+#define HW_STM32L4X5_GPIO_H
+
+#include "hw/sysbus.h"
+#include "qom/object.h"
+
+#define TYPE_STM32L4X5_GPIO "stm32l4x5-gpio"
+#define TYPE_STM32L4X5_GPIO_A "stm32l4x5-gpio-a"
+#define TYPE_STM32L4X5_GPIO_B "stm32l4x5-gpio-b"
+#define TYPE_STM32L4X5_GPIO_C "stm32l4x5-gpio-c"
+#define TYPE_STM32L4X5_GPIO_D "stm32l4x5-gpio-d"
+#define TYPE_STM32L4X5_GPIO_E "stm32l4x5-gpio-e"
+#define TYPE_STM32L4X5_GPIO_F "stm32l4x5-gpio-f"
+#define TYPE_STM32L4X5_GPIO_G "stm32l4x5-gpio-g"
+#define TYPE_STM32L4X5_GPIO_H "stm32l4x5-gpio-h"
+OBJECT_DECLARE_TYPE(Stm32l4x5GpioState, Stm32l4x5GpioClass, STM32L4X5_GPIO)
+
+#define GPIO_NUM_PINS 16
+
+struct Stm32l4x5GpioState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion mmio;
+
+ /* GPIO registers */
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t idr;
+ uint32_t odr;
+ uint32_t lckr;
+ uint32_t afrl;
+ uint32_t afrh;
+ uint32_t ascr;
+
+ /*
+ * External driving of pins.
+ * The pins can be set externally through the device
+ * anonymous input GPIOs lines under certain conditions.
+ * The pin must not be in push-pull output mode,
+ * and can't be set high in open-drain mode.
+ * Pins driven externally and configured to
+ * output mode will in general be "disconnected"
+ * (see `get_gpio_pins_to_disconnect()`)
+ */
+ uint16_t disconnected_pins;
+ uint16_t pins_connected_high;
+
+ qemu_irq pin[GPIO_NUM_PINS];
+};
+
+struct Stm32l4x5GpioClass {
+ SysBusDeviceClass parent_class;
+
+ uint32_t moder_reset;
+ uint32_t ospeedr_reset;
+ uint32_t pupdr_reset;
+};
+
+#endif