@@ -36,7 +36,7 @@
bool riscv_is_32bit(RISCVHartArrayState *harts)
{
- return harts->harts[0].env.misa_mxl_max == MXL_RV32;
+ return riscv_array_get_hart(harts, 0)->env.misa_mxl_max == MXL_RV32;
}
/*
@@ -190,8 +190,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp)
NICInfo *nd;
int i;
- sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
+ riscv_hart_array_realize(&s->e_cpus, &error_abort);
+ riscv_hart_array_realize(&s->u_cpus, &error_abort);
/*
* The cluster must be realized after the RISC-V hart array container,
* as the container's CPU object is only created on realize, and the
@@ -135,7 +135,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
&error_abort);
object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
+ riscv_hart_array_realize(&s->cpus, &error_abort);
/* Boot ROM */
memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
@@ -108,7 +108,7 @@ static void shakti_c_soc_state_realize(DeviceState *dev, Error **errp)
ShaktiCSoCState *sss = RISCV_SHAKTI_SOC(dev);
MemoryRegion *system_memory = get_system_memory();
- sysbus_realize(SYS_BUS_DEVICE(&sss->cpus), &error_abort);
+ riscv_hart_array_realize(&sss->cpus, &error_abort);
sss->plic = sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base,
(char *)SHAKTI_C_PLIC_HART_CONFIG, ms->smp.cpus, 0,
@@ -195,7 +195,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type,
&error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort);
+ riscv_hart_array_realize(&s->cpus, &error_abort);
/* Mask ROM */
memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
@@ -188,9 +188,9 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap,
} else {
qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48");
}
- isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]);
+ isa = riscv_isa_string(riscv_array_get_hart(&s->soc.u_cpus, cpu - 1));
} else {
- isa = riscv_isa_string(&s->soc.e_cpus.harts[0]);
+ isa = riscv_isa_string(riscv_array_get_hart(&s->soc.e_cpus, 0));
}
qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv");
@@ -830,8 +830,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", s->cpu_type);
qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004);
- sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort);
- sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort);
+ riscv_hart_array_realize(&s->e_cpus, &error_abort);
+ riscv_hart_array_realize(&s->u_cpus, &error_abort);
/*
* The cluster must be realized after the RISC-V hart array container,
* as the container's CPU object is only created on realize, and the
+ Use riscv_array_get_hart instead of accessing harts field. + Use riscv_hart_array_realize instead of sysbus_realize. spike and virt machines will be handled separately in following commits. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> --- hw/riscv/boot.c | 2 +- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/opentitan.c | 2 +- hw/riscv/shakti_c.c | 2 +- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 8 ++++---- 6 files changed, 10 insertions(+), 10 deletions(-)