@@ -41,4 +41,23 @@ struct RISCVHartArrayState {
RISCVCPU *harts;
};
+/**
+ * riscv_array_get_hart:
+ */
+static inline RISCVCPU *riscv_array_get_hart(RISCVHartArrayState *harts, int i)
+{
+ return &harts->harts[i];
+}
+
+/**
+ * riscv_array_get_num_harts:
+ */
+static inline unsigned riscv_array_get_num_harts(RISCVHartArrayState *harts)
+{
+ return harts->num_harts;
+}
+
+/* Temporary function until we migrated the riscv hart array to simple device */
+void riscv_hart_array_realize(RISCVHartArrayState *state, Error **errp);
+
#endif
@@ -27,6 +27,11 @@
#include "hw/qdev-properties.h"
#include "hw/riscv/riscv_hart.h"
+void riscv_hart_array_realize(RISCVHartArrayState *state, Error **errp)
+{
+ sysbus_realize(SYS_BUS_DEVICE(state), errp);
+}
+
static Property riscv_harts_props[] = {
DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
riscv_hart_array does not need to be a sysbus device: it does not have any mmio or sysbus irq. We want to make it inherit the new cpus class so we need a few tweaks: + a temporary helper realize so we can switch from sysbus_realize to qdev_realize (will be removed afer the transition is done). + a helper function to get an hart from the array (the current storage array field will be removed). + a helper function to get the number of harts in an array (the current field will be removed). Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> --- include/hw/riscv/riscv_hart.h | 19 +++++++++++++++++++ hw/riscv/riscv_hart.c | 5 +++++ 2 files changed, 24 insertions(+)