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[193.152.124.33]) by smtp.gmail.com with ESMTPSA id s189sm9632538wme.0.2021.12.23.04.00.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Dec 2021 04:00:18 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 19/23] hw/scsi/megasas: Use uint32_t for reply queue head/tail values Date: Thu, 23 Dec 2021 12:55:50 +0100 Message-Id: <20211223115554.3155328-20-philmd@redhat.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211223115554.3155328-1-philmd@redhat.com> References: <20211223115554.3155328-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=170.10.129.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -29 X-Spam_score: -3.0 X-Spam_bar: --- X-Spam_report: (-3.0 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.203, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Dmitry Fleytman , "Michael S. Tsirkin" , Jason Wang , Bin Meng , David Hildenbrand , Peter Xu , Gerd Hoffmann , Klaus Jensen , "Edgar E. Iglesias" , Sven Schnelle , Hannes Reinecke , qemu-block@nongnu.org, Daniel Henrique Barboza , Havard Skinnemoen , Joel Stanley , Stefan Weil , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Mark Cave-Ayland , Alistair Francis , Richard Henderson , Greg Kurz , Beniamino Galvani , Eric Auger , qemu-arm@nongnu.org, Jan Kiszka , =?utf-8?q?C=C3=A9dric_?= =?utf-8?q?Le_Goater?= , Keith Busch , John Snow , David Gibson , Eduardo Habkost , Andrew Jeffery , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann , Tyrone Ting , qemu-ppc@nongnu.org, Paolo Bonzini Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" While the reply queue values fit in 16-bit, they are accessed as 32-bit: 661: s->reply_queue_head = ldl_le_pci_dma(pcid, s->producer_pa); 662: s->reply_queue_head %= MEGASAS_MAX_FRAMES; 663: s->reply_queue_tail = ldl_le_pci_dma(pcid, s->consumer_pa); 664: s->reply_queue_tail %= MEGASAS_MAX_FRAMES; Having: 41:#define MEGASAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */ In order to update the ld/st*_pci_dma() API to pass the address of the value to access, it is simpler to have the head/tail declared as 32-bit values. Replace the uint16_t by uint32_t, wasting 4 bytes in the MegasasState structure. Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- hw/scsi/megasas.c | 4 ++-- hw/scsi/trace-events | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index 87101705d01..266c3d38003 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -109,8 +109,8 @@ struct MegasasState { uint64_t reply_queue_pa; void *reply_queue; uint16_t reply_queue_len; - uint16_t reply_queue_head; - uint16_t reply_queue_tail; + uint32_t reply_queue_head; + uint32_t reply_queue_tail; uint64_t consumer_pa; uint64_t producer_pa; diff --git a/hw/scsi/trace-events b/hw/scsi/trace-events index 92d5b40f892..ae8551f2797 100644 --- a/hw/scsi/trace-events +++ b/hw/scsi/trace-events @@ -42,18 +42,18 @@ mptsas_config_sas_phy(void *dev, int address, int port, int phy_handle, int dev_ # megasas.c megasas_init_firmware(uint64_t pa) "pa 0x%" PRIx64 " " -megasas_init_queue(uint64_t queue_pa, int queue_len, uint64_t head, uint64_t tail, uint32_t flags) "queue at 0x%" PRIx64 " len %d head 0x%" PRIx64 " tail 0x%" PRIx64 " flags 0x%x" +megasas_init_queue(uint64_t queue_pa, int queue_len, uint32_t head, uint32_t tail, uint32_t flags) "queue at 0x%" PRIx64 " len %d head 0x%" PRIx32 " tail 0x%" PRIx32 " flags 0x%x" megasas_initq_map_failed(int frame) "scmd %d: failed to map queue" megasas_initq_mapped(uint64_t pa) "queue already mapped at 0x%" PRIx64 megasas_initq_mismatch(int queue_len, int fw_cmds) "queue size %d max fw cmds %d" megasas_qf_mapped(unsigned int index) "skip mapped frame 0x%x" megasas_qf_new(unsigned int index, uint64_t frame) "frame 0x%x addr 0x%" PRIx64 megasas_qf_busy(unsigned long pa) "all frames busy for frame 0x%lx" -megasas_qf_enqueue(unsigned int index, unsigned int count, uint64_t context, unsigned int head, unsigned int tail, int busy) "frame 0x%x count %d context 0x%" PRIx64 " head 0x%x tail 0x%x busy %d" -megasas_qf_update(unsigned int head, unsigned int tail, unsigned int busy) "head 0x%x tail 0x%x busy %d" +megasas_qf_enqueue(unsigned int index, unsigned int count, uint64_t context, uint32_t head, uint32_t tail, unsigned int busy) "frame 0x%x count %d context 0x%" PRIx64 " head 0x%" PRIx32 " tail 0x%" PRIx32 " busy %u" +megasas_qf_update(uint32_t head, uint32_t tail, unsigned int busy) "head 0x%" PRIx32 " tail 0x%" PRIx32 " busy %u" megasas_qf_map_failed(int cmd, unsigned long frame) "scmd %d: frame %lu" megasas_qf_complete_noirq(uint64_t context) "context 0x%" PRIx64 " " -megasas_qf_complete(uint64_t context, unsigned int head, unsigned int tail, int busy) "context 0x%" PRIx64 " head 0x%x tail 0x%x busy %d" +megasas_qf_complete(uint64_t context, uint32_t head, uint32_t tail, int busy) "context 0x%" PRIx64 " head 0x%" PRIx32 " tail 0x%" PRIx32 " busy %u" megasas_frame_busy(uint64_t addr) "frame 0x%" PRIx64 " busy" megasas_unhandled_frame_cmd(int cmd, uint8_t frame_cmd) "scmd %d: MFI cmd 0x%x" megasas_handle_scsi(const char *frame, int bus, int dev, int lun, void *sdev, unsigned long size) "%s dev %x/%x/%x sdev %p xfer %lu"