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[83.52.55.163]) by smtp.gmail.com with ESMTPSA id r1sm15831189wrt.24.2021.08.23.09.42.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Aug 2021 09:42:12 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 3/5] exec/memattrs: Introduce MemTxAttrs::bus_perm field Date: Mon, 23 Aug 2021 18:41:55 +0200 Message-Id: <20210823164157.751807-4-philmd@redhat.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20210823164157.751807-1-philmd@redhat.com> References: <20210823164157.751807-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Received-SPF: pass client-ip=216.205.24.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -34 X-Spam_score: -3.5 X-Spam_bar: --- X-Spam_report: (-3.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.743, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , David Hildenbrand , Jason Wang , Li Qiang , Qiuhao Li , Peter Xu , Alexander Bulekov , qemu-arm@nongnu.org, Gerd Hoffmann , Stefan Hajnoczi , Paolo Bonzini , "Edgar E . Iglesias" , =?utf-8?q?Philippe_Mathieu?= =?utf-8?q?-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add the 'direct_access' bit to the memory attributes to restrict bus master access to ROM/RAM. Have read/write accessors return MEMTX_BUS_ERROR if an access is restricted and the region is not ROM/RAM ('direct'). Add corresponding trace events. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/memattrs.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 95f2d20d55b..7a94ee75a88 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -14,6 +14,13 @@ #ifndef MEMATTRS_H #define MEMATTRS_H +/* Permission to restrict bus memory accesses. See MemTxAttrs::bus_perm */ +enum { + MEMTXPERM_UNSPECIFIED = 0, + MEMTXPERM_UNRESTRICTED = 1, + MEMTXPERM_RAM_DEVICE = 2, +}; + /* Every memory transaction has associated with it a set of * attributes. Some of these are generic (such as the ID of * the bus master); some are specific to a particular kind of @@ -35,6 +42,19 @@ typedef struct MemTxAttrs { unsigned int secure:1; /* Memory access is usermode (unprivileged) */ unsigned int user:1; + /* + * Bus memory access permission. + * + * Some devices (such DMA) might be restricted to only access + * some type of device, such RAM devices. By default memory + * accesses are unspecified (MEMTXPERM_UNSPECIFIED), but could be + * unrestricted (MEMTXPERM_UNRESTRICTED, similar to an allow list) + * or restricted to a type of devices (similar to a deny list). + * Currently only RAM devices can be restricted (MEMTXPERM_RAM_DEVICE). + * + * Memory accesses to restricted addresses return MEMTX_BUS_ERROR. + */ + unsigned int bus_perm:2; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; /* Invert endianness for this page */ @@ -66,6 +86,7 @@ typedef struct MemTxAttrs { #define MEMTX_OK 0 #define MEMTX_ERROR (1U << 0) /* device returned an error */ #define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */ +#define MEMTX_BUS_ERROR (1U << 2) /* bus returned an error */ typedef uint32_t MemTxResult; #endif