@@ -1,3 +1,6 @@
+config RISCV_NUMA
+ bool
+
config IBEX
bool
@@ -34,6 +37,7 @@ config RISCV_VIRT
imply PCI_DEVICES
imply VIRTIO_VGA
imply TEST_DEVICES
+ select RISCV_NUMA
select GOLDFISH_RTC
select MSI_NONBROKEN
select PCI
@@ -74,6 +78,7 @@ config SIFIVE_U
config SPIKE
bool
+ select RISCV_NUMA
select HTIF
select MSI_NONBROKEN
select SIFIVE_CLINT
@@ -1,6 +1,6 @@
riscv_ss = ss.source_set()
riscv_ss.add(files('boot.c'), fdt)
-riscv_ss.add(files('numa.c'))
+riscv_ss.add(when: 'CONFIG_RISCV_NUMA', if_true: files('numa.c'))
riscv_ss.add(files('riscv_hart.c'))
riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c'))
riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c'))