diff mbox series

[PULL,v1,1/3] target/cris: Use MMUAccessType enum type when possible

Message ID 20210222083324.331908-2-edgar.iglesias@gmail.com
State New
Headers show
Series [PULL,v1,1/3] target/cris: Use MMUAccessType enum type when possible | expand

Commit Message

Edgar E. Iglesias Feb. 22, 2021, 8:33 a.m. UTC 
From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Replace the 0/1/2 magic values by the corresponding MMUAccessType.
We can remove a comment as enum names are self explicit.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <20210128003223.3561108-2-f4bug@amsat.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/cris/helper.c |  4 ++--
 target/cris/mmu.c    | 13 ++++++-------
 2 files changed, 8 insertions(+), 9 deletions(-)
diff mbox series

Patch

diff --git a/target/cris/helper.c b/target/cris/helper.c
index 7e3bb58fe1..911867f3b4 100644
--- a/target/cris/helper.c
+++ b/target/cris/helper.c
@@ -275,10 +275,10 @@  hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     struct cris_mmu_result res;
     int miss;
 
-    miss = cris_mmu_translate(&res, &cpu->env, addr, 0, 0, 1);
+    miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_DATA_LOAD, 0, 1);
     /* If D TLB misses, try I TLB.  */
     if (miss) {
-        miss = cris_mmu_translate(&res, &cpu->env, addr, 2, 0, 1);
+        miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_INST_FETCH, 0, 1);
     }
 
     if (!miss) {
diff --git a/target/cris/mmu.c b/target/cris/mmu.c
index a279b7f1b6..294de7dffd 100644
--- a/target/cris/mmu.c
+++ b/target/cris/mmu.c
@@ -152,15 +152,15 @@  static int cris_mmu_translate_page(struct cris_mmu_result *res,
     pid = env->pregs[PR_PID] & 0xff;
 
     switch (rw) {
-    case 2:
+    case MMU_INST_FETCH:
         rwcause = CRIS_MMU_ERR_EXEC;
         mmu = 0;
         break;
-    case 1:
+    case MMU_DATA_STORE:
         rwcause = CRIS_MMU_ERR_WRITE;
         break;
     default:
-    case 0:
+    case MMU_DATA_LOAD:
         rwcause = CRIS_MMU_ERR_READ;
         break;
     }
@@ -219,13 +219,13 @@  static int cris_mmu_translate_page(struct cris_mmu_result *res,
                      vaddr, lo, env->pc));
             match = 0;
             res->bf_vec = vect_base + 2;
-        } else if (rw == 1 && cfg_w && !tlb_w) {
+        } else if (rw == MMU_DATA_STORE && cfg_w && !tlb_w) {
             D(printf("tlb: write protected %x lo=%x pc=%x\n",
                      vaddr, lo, env->pc));
             match = 0;
             /* write accesses never go through the I mmu.  */
             res->bf_vec = vect_base + 3;
-        } else if (rw == 2 && cfg_x && !tlb_x) {
+        } else if (rw == MMU_INST_FETCH && cfg_x && !tlb_x) {
             D(printf("tlb: exec protected %x lo=%x pc=%x\n",
                      vaddr, lo, env->pc));
             match = 0;
@@ -329,8 +329,7 @@  int cris_mmu_translate(struct cris_mmu_result *res,
 
     old_srs = env->pregs[PR_SRS];
 
-    /* rw == 2 means exec, map the access to the insn mmu.  */
-    env->pregs[PR_SRS] = rw == 2 ? 1 : 2;
+    env->pregs[PR_SRS] = rw == MMU_INST_FETCH ? 1 : 2;
 
     if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) {
         res->phy = vaddr;