From patchwork Sat Oct 10 13:57:58 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luc Michel X-Patchwork-Id: 1380047 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=lmichel.fr Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=lmichel.fr header.i=@lmichel.fr header.a=rsa-sha256 header.s=pharaoh header.b=VyKGCN5Q; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C7msF40gMz9sT6 for ; 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bh=MO0Muj7yuPd6SWwH9hfY/l2s1zABrTHCErTOwR/d+QM=; b=VyKGCN5QIjRI7lfg0PhLOl/QWGjzATW1evA45KI0zttBsY+wX8+tVXB6HUw7eGHA+ezxJu LRASA7I4JrKTk01ee8UvEI3X8ZkbojiWGIEKDJOgtc8w0meN1t1npHzORFHdM6WQBKaKGk 1zwdTZYs0dZRwXj7G+DTqUTPFe4j1wCgNjJL54oHO5LnOMGX5+bnIra4TxzHad6p2o/hnR nZzDfWx7WBGHS9gzPgH2IgXfhj88ewRVTV0VfmigESOmrbq/yQX4EtEkmTb+LrvLLIeGtD 96Ud+QVb01EUE58ZAwYGtrksGHbK4Gu7OSeNedgdoGiLP902MdBvSgYIRaylxQ== From: Luc Michel To: qemu-devel@nongnu.org Subject: [PATCH v3 14/15] hw/char/pl011: add a clock input Date: Sat, 10 Oct 2020 15:57:58 +0200 Message-Id: <20201010135759.437903-15-luc@lmichel.fr> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201010135759.437903-1-luc@lmichel.fr> References: <20201010135759.437903-1-luc@lmichel.fr> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1602338225; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; 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This is intended for developers who wish to use QEMU to e.g. debug their firmware or to figure out the baud rate configured by an unknown/closed source binary. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Luc Michel --- include/hw/char/pl011.h | 1 + hw/char/pl011.c | 45 +++++++++++++++++++++++++++++++++++++++++ hw/char/trace-events | 1 + 3 files changed, 47 insertions(+) diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h index a91ea50e11..33e5e5317b 100644 --- a/include/hw/char/pl011.h +++ b/include/hw/char/pl011.h @@ -47,10 +47,11 @@ struct PL011State { int read_pos; int read_count; int read_trigger; CharBackend chr; qemu_irq irq[6]; + Clock *clk; const unsigned char *id; }; static inline DeviceState *pl011_create(hwaddr addr, qemu_irq irq, diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 13e784f9d9..ede16c781c 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -20,10 +20,11 @@ #include "qemu/osdep.h" #include "hw/char/pl011.h" #include "hw/irq.h" #include "hw/sysbus.h" +#include "hw/qdev-clock.h" #include "migration/vmstate.h" #include "chardev/char-fe.h" #include "qemu/log.h" #include "qemu/module.h" #include "trace.h" @@ -167,10 +168,29 @@ static void pl011_set_read_trigger(PL011State *s) else #endif s->read_trigger = 1; } +static unsigned int pl011_get_baudrate(const PL011State *s) +{ + uint64_t clk; + + if (s->fbrd == 0) { + return 0; + } + + clk = clock_get_hz(s->clk); + return (clk / ((s->ibrd << 6) + s->fbrd)) << 2; +} + +static void pl011_trace_baudrate_change(const PL011State *s) +{ + trace_pl011_baudrate_change(pl011_get_baudrate(s), + clock_get_hz(s->clk), + s->ibrd, s->fbrd); +} + static void pl011_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { PL011State *s = (PL011State *)opaque; unsigned char ch; @@ -196,13 +216,15 @@ static void pl011_write(void *opaque, hwaddr offset, case 8: /* UARTUARTILPR */ s->ilpr = value; break; case 9: /* UARTIBRD */ s->ibrd = value; + pl011_trace_baudrate_change(s); break; case 10: /* UARTFBRD */ s->fbrd = value; + pl011_trace_baudrate_change(s); break; case 11: /* UARTLCR_H */ /* Reset the FIFO state on FIFO enable or disable */ if ((s->lcr ^ value) & 0x10) { s->read_count = 0; @@ -284,16 +306,33 @@ static void pl011_event(void *opaque, QEMUChrEvent event) { if (event == CHR_EVENT_BREAK) pl011_put_fifo(opaque, 0x400); } +static void pl011_clock_update(void *opaque) +{ + PL011State *s = PL011(opaque); + + pl011_trace_baudrate_change(s); +} + static const MemoryRegionOps pl011_ops = { .read = pl011_read, .write = pl011_write, .endianness = DEVICE_NATIVE_ENDIAN, }; +static const VMStateDescription vmstate_pl011_clock = { + .name = "pl011/clock", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_CLOCK(clk, PL011State), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_pl011 = { .name = "pl011", .version_id = 2, .minimum_version_id = 2, .fields = (VMStateField[]) { @@ -312,10 +351,14 @@ static const VMStateDescription vmstate_pl011 = { VMSTATE_UINT32(ifl, PL011State), VMSTATE_INT32(read_pos, PL011State), VMSTATE_INT32(read_count, PL011State), VMSTATE_INT32(read_trigger, PL011State), VMSTATE_END_OF_LIST() + }, + .subsections = (const VMStateDescription * []) { + &vmstate_pl011_clock, + NULL } }; static Property pl011_properties[] = { DEFINE_PROP_CHR("chardev", PL011State, chr), @@ -332,10 +375,12 @@ static void pl011_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); for (i = 0; i < ARRAY_SIZE(s->irq); i++) { sysbus_init_irq(sbd, &s->irq[i]); } + s->clk = qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, s); + s->read_trigger = 1; s->ifl = 0x12; s->cr = 0x300; s->flags = 0x90; diff --git a/hw/char/trace-events b/hw/char/trace-events index 609df10fed..81026f6612 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -63,10 +63,11 @@ pl011_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" pl011_read_fifo(int read_count) "FIFO read, read_count now %d" pl011_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d" pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %d" pl011_put_fifo_full(void) "FIFO now full, RXFF set" +pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd, uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", fbrd: %" PRIu32 ")" # cmsdk-apb-uart.c cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB UART read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" cmsdk_apb_uart_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK APB UART write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" cmsdk_apb_uart_reset(void) "CMSDK APB UART: reset"