From patchwork Mon Oct 5 19:56:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Luc Michel X-Patchwork-Id: 1376985 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=lmichel.fr Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; secure) header.d=lmichel.fr header.i=@lmichel.fr header.a=rsa-sha256 header.s=pharaoh header.b=NSIREmTx; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4C4vpk0xMwz9sVL for ; Tue, 6 Oct 2020 09:07:26 +1100 (AEDT) Received: from localhost ([::1]:44838 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kPX0k-0007Jm-Ir for incoming@patchwork.ozlabs.org; Mon, 05 Oct 2020 16:23:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:57844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kPWaH-0004y7-TG; Mon, 05 Oct 2020 15:55:45 -0400 Received: from pharaoh.lmichel.fr ([149.202.28.74]:35982) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kPWaG-0007ZX-14; Mon, 05 Oct 2020 15:55:45 -0400 Received: from sekoia-pc.home.lmichel.fr (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPS id 006A1C60F1B; Mon, 5 Oct 2020 19:55:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1601927720; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sXZbbcIcfJa9fmuyQ/jkFubTz3/tLARdyvfrI2boCtg=; b=NSIREmTxom20lxgcpeVoX620QlQ+XM9XQnrLwl0sdMgU5dQOIYwd3QfInbt+Wv11H2VNjX r4OkHA/a9ZVi/QlmpCeptTF9iMyZEMoPqSV96mY5UcWeX8USz4cFX2SAX0mmUUjCWJZfi3 sTfrvXnDMROEnkBFPXtW9SX6IgKosRcMKYUjExA2q+MXhIJxIBpEfWp0lufCWnSh5lDwtq TUQu28CyjPYGCE/JESCKTxqtsGvS0NZ3D5uzSfTmTQU8EAj5xB7EhQYH8l/JFHSAnyou78 vE3T7Df5zf+ren8ROQjDXpoP1qa/S26/cy1xG2Fj8cUJ2Ix4e8sBsfEQGrqdlQ== From: Luc Michel To: qemu-devel@nongnu.org Subject: [PATCH v2 11/15] hw/misc/bcm2835_cprman: implement clock mux behaviour Date: Mon, 5 Oct 2020 21:56:08 +0200 Message-Id: <20201005195612.1999165-12-luc@lmichel.fr> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201005195612.1999165-1-luc@lmichel.fr> References: <20201005195612.1999165-1-luc@lmichel.fr> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1601927720; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=sXZbbcIcfJa9fmuyQ/jkFubTz3/tLARdyvfrI2boCtg=; b=cuaktJghC3KIS8Q4gEWOvwQ7F8Ez/oG/QosnmU1raegC/jsWJyeRW9lSO54XmKL5oMJ7d8 MkKLzdG1qClFzkTNCwPYAIiNehdIhwnlelSwCvIqz9ihU1TBPHL73ctKNb/T8Yy4vP9IZe unTM4vziHQ8M7T3UwUsjv0oEoaKGhQQbIi3TB/r1kPcW1cqcphmme/k3t8tEQJY0Rd7Lu1 ONwE+zPGfHCtY4QlzH4yBYo4ZQ5Fb9ZNltkkiBY/ERwxmV2+ts8UyOTdW7ejktZq4PuYz6 RxY9usIA+wp0VqYOzPmvZRIrJ+TY6cDY9zpW/LCjgIs5AjJNr213xVTt/sHUKg== ARC-Seal: i=1; s=pharaoh; d=lmichel.fr; t=1601927720; a=rsa-sha256; cv=none; b=EeNOZrywYdSfvZajZ+tAE07XNrtZDue3TqKIMOmgUARksP12jX72OWOCj5759fuKT7DPYh/z67cw6zvhfguCSlSbVrtl8Ms7q1wMRiwPEX5FrxO0Tm3tC8Ij7oIhda7KVUgLiT4UAAjWL4Mv0laHSyYe5f4TzOTTdnv35PzrFdVsoxRCs4rm12hM43sp6+aifBWma6/t2BcVjGBih/Xt2aEjT32ogiV7zMHlXZ5veN06C/j0mpr3qtaR84luH5+4m0KCTcB0QSVJnBfdG7ychQ9eRiBStBgLN2XlW26cw25IFudOje3LhY72w/tYzQOs8VR/g81eJVdZ/GpvoBfoeQ== ARC-Authentication-Results: i=1; pharaoh.lmichel.fr Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/05 15:49:50 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Luc Michel , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann , Paul Zimmerman , Niek Linnenbank , qemu-arm@nongnu.org, Havard Skinnemoen Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" A clock mux can be configured to select one of its 10 sources through the CM_CTL register. It also embeds yet another clock divider, composed of an integer part and a fractional part. The number of bits of each part is mux dependent. Tested-by: Philippe Mathieu-Daudé Signed-off-by: Luc Michel --- hw/misc/bcm2835_cprman.c | 44 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index a470ce2026..7d59423367 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -229,19 +229,61 @@ static const TypeInfo cprman_pll_channel_info = { }; /* clock mux */ +static bool clock_mux_is_enabled(CprmanClockMuxState *mux) +{ + return FIELD_EX32(*mux->reg_cm, CM_CLOCKx_CTL, ENABLE); +} + static void clock_mux_update(CprmanClockMuxState *mux) { - clock_update(mux->out, 0); + uint64_t freq; + uint32_t div, src = FIELD_EX32(*mux->reg_cm, CM_CLOCKx_CTL, SRC); + bool enabled = clock_mux_is_enabled(mux); + + *mux->reg_cm = FIELD_DP32(*mux->reg_cm, CM_CLOCKx_CTL, BUSY, enabled); + + if (!enabled) { + clock_update(mux->out, 0); + return; + } + + freq = clock_get_hz(mux->srcs[src]); + + if (mux->int_bits == 0 && mux->frac_bits == 0) { + clock_update_hz(mux->out, freq); + return; + } + + /* + * The divider has an integer and a fractional part. The size of each part + * varies with the muxes (int_bits and frac_bits). Both parts are + * concatenated, with the integer part always starting at bit 12. + */ + div = mux->reg_cm[1] >> (R_CM_CLOCKx_DIV_FRAC_LENGTH - mux->frac_bits); + div &= (1 << (mux->int_bits + mux->frac_bits)) - 1; + + if (!div) { + clock_update(mux->out, 0); + } + + freq = muldiv64(freq, 1 << mux->frac_bits, div); + + clock_update_hz(mux->out, freq); } static void clock_mux_src_update(void *opaque) { CprmanClockMuxState **backref = opaque; CprmanClockMuxState *s = *backref; + CprmanClockMuxSource src = backref - s->backref; + + if (FIELD_EX32(*s->reg_cm, CM_CLOCKx_CTL, SRC) != src) { + return; + } clock_mux_update(s); } static void clock_mux_init(Object *obj)