diff mbox series

[PULL,v1,11/14] target/microblaze: Fix FPU2 instruction check

Message ID 20200514141402.12498-12-edgar.iglesias@gmail.com
State New
Headers show
Series [PULL,v1,01/14] hw/net/xilinx_axienet: Auto-clear PHY Autoneg | expand

Commit Message

Edgar E. Iglesias May 14, 2020, 2:13 p.m. UTC 
From: Joe Komlodi <joe.komlodi@xilinx.com>

The check to see if we can use FPU2 instructions would return 0 if
cfg.use_fpu == 2, rather than returning the PVR2_USE_FPU2_MASK.

This would cause all FPU2 instructions (fsqrt, flt, fint) to not be used.

Signed-off-by: Joe Komlodi <komlodi@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <1589219346-106769-2-git-send-email-komlodi@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 92b3630804..8079724f32 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1392,7 +1392,7 @@  static int dec_check_fpuv2(DisasContext *dc)
         tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_FPU);
         t_gen_raise_exception(dc, EXCP_HW_EXCP);
     }
-    return (dc->cpu->cfg.use_fpu == 2) ? 0 : PVR2_USE_FPU2_MASK;
+    return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0;
 }
 
 static void dec_fpu(DisasContext *dc)