diff mbox series

[v1,1/1] target/microblaze: Add MFS Rd,EDR translation

Message ID 20200512143649.21655-2-edgar.iglesias@gmail.com
State New
Headers show
Series target/microblaze: Fix mfs from EDR | expand

Commit Message

Edgar E. Iglesias May 12, 2020, 2:36 p.m. UTC 
From: Tong Ho <tong.ho@xilinx.com>

This is to fix cpu-abort with 'qemu: fatal: unknown mfs reg d'
(in the default case) when microblaze guest issues 'MFS Rd,EDR'
instruction.

Since embeddedsw release 2019.2, XPlm_ExceptionHandler() issues
the instruction on exception, and microblaze model aborts when
PLM firmware guest encounters an exception.

Signed-off-by: Tong Ho <tong.ho@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Luc Michel May 13, 2020, 7:42 a.m. UTC | #1 
On 5/12/20 4:36 PM, Edgar E. Iglesias wrote:
> From: Tong Ho <tong.ho@xilinx.com>
> 
> This is to fix cpu-abort with 'qemu: fatal: unknown mfs reg d'
> (in the default case) when microblaze guest issues 'MFS Rd,EDR'
> instruction.
> 
> Since embeddedsw release 2019.2, XPlm_ExceptionHandler() issues
> the instruction on exception, and microblaze model aborts when
> PLM firmware guest encounters an exception.
> 
> Signed-off-by: Tong Ho <tong.ho@xilinx.com>
> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Luc Michel <luc.michel@greensocs.com>

> ---
>  target/microblaze/translate.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 20b7427811..92b3630804 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -581,6 +581,7 @@ static void dec_msr(DisasContext *dc)
>              case SR_ESR:
>              case SR_FSR:
>              case SR_BTR:
> +            case SR_EDR:
>                  tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_SR[sr]);
>                  break;
>              case 0x800:
>
diff mbox series

Patch

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 20b7427811..92b3630804 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -581,6 +581,7 @@  static void dec_msr(DisasContext *dc)
             case SR_ESR:
             case SR_FSR:
             case SR_BTR:
+            case SR_EDR:
                 tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_SR[sr]);
                 break;
             case 0x800: