From patchwork Mon Jul 29 14:56:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Damien Hedde X-Patchwork-Id: 1138478 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=greensocs.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=greensocs.com header.i=@greensocs.com header.b="Ea3nNUHB"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 45y3Kb4M1Hz9s7T for ; Tue, 30 Jul 2019 01:20:35 +1000 (AEST) Received: from localhost ([::1]:53566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hs7Rx-0002PX-Mv for incoming@patchwork.ozlabs.org; Mon, 29 Jul 2019 11:20:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39847) by lists.gnu.org with esmtp (Exim 4.86_2) (envelope-from ) id 1hs79E-0007Vr-Qs for qemu-devel@nongnu.org; Mon, 29 Jul 2019 11:01:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hs79C-0006fi-TC for qemu-devel@nongnu.org; Mon, 29 Jul 2019 11:01:12 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:49068) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1hs78x-0005ZI-5J; Mon, 29 Jul 2019 11:00:55 -0400 Received: from kouign-amann.bar.greensocs.com (unknown [172.16.11.117]) by beetle.greensocs.com (Postfix) with ESMTPS id 9260497064; Mon, 29 Jul 2019 14:59:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1564412372; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=N5wnMQEiMoszMl9iY43hRAj3emLdaJgse3RhUORv7mA=; b=Ea3nNUHBhop4jRADSkdTGq8pqTrpXz8GjNAW2XOEMWXYWs4wr6y+Azhd+x6TyzmtaUIa0f fgu1C6oh+49Zae93jKY13Chv48FFAG3Hs8IcWm1SPNlfFxrUNTNdC2Y2qBXqIs5eoB5Aql U8JHbKOijurENUbWe5wZMFcIbObAerg= From: Damien Hedde To: qemu-devel@nongnu.org Date: Mon, 29 Jul 2019 16:56:51 +0200 Message-Id: <20190729145654.14644-31-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: <20190729145654.14644-1-damien.hedde@greensocs.com> References: <20190729145654.14644-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1564412372; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=N5wnMQEiMoszMl9iY43hRAj3emLdaJgse3RhUORv7mA=; b=WvAtHFZsfTFPAyXrEStEy1QIY3iaOPPwetox0EZF1ouGR0iZA29+tV6sRjebYFOKLBM57J ERM5gqfvLMean5HO212vrYh/lF0WaUMObYwSA6zV0lo4Lujk1Y4YMrytvg7FPQJZD2FcFs x4N1AhQyvYa7aPdtUtQX/lfy7Hiuxb4= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1564412372; a=rsa-sha256; cv=none; b=yqKxTNzhj6/OkXaMKs3th7yRmN8RS62X4Voqti9rlDfKpu/d7N7Kgr3wUUWvZGqQx7x4hi l52Z15Xyv0LQzYmMskkshTZNNPaqY3YL/Bt+Bc5Tx19zVqit+2xIay0hRixEs7vchqGlf2 Cas3a3jnxOwoJBCjeOsNz1N+84QeNVE= ARC-Authentication-Results: i=1; beetle.greensocs.com; none X-Spam: Yes X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 Subject: [Qemu-devel] [PATCH v3 30/33] convert cadence_uart to 3-phases reset X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: fam@euphon.net, peter.maydell@linaro.org, walling@linux.ibm.com, dmitry.fleytman@gmail.com, mst@redhat.com, mark.cave-ayland@ilande.co.uk, kraxel@redhat.com, edgar.iglesias@xilinx.com, hare@suse.com, qemu-block@nongnu.org, david@redhat.com, pasic@linux.ibm.com, borntraeger@de.ibm.com, marcandre.lureau@redhat.com, rth@twiddle.net, thuth@redhat.com, ehabkost@redhat.com, alistair@alistair23.me, qemu-s390x@nongnu.org, qemu-arm@nongnu.org, clg@kaod.org, jsnow@redhat.com, david@gibson.dropbear.id.au, Damien Hedde , berrange@redhat.com, cohuck@redhat.com, mark.burton@greensocs.com, qemu-ppc@nongnu.org, pbonzini@redhat.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Split the existing reset procedure into 3 phases. Test the resetting flag to discard register accesses and character reception. Also adds a active high reset io. Signed-off-by: Damien Hedde --- hw/char/cadence_uart.c | 77 +++++++++++++++++++++++++++++++++++++++--- 1 file changed, 73 insertions(+), 4 deletions(-) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index fa25fe24da..d7bacc44fe 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -39,6 +39,18 @@ #define DB_PRINT(...) #endif +#define CADENCE_UART_CLASS(class) \ + OBJECT_CLASS_CHECK(CadenceUartClass, (class), TYPE_CADENCE_UART) +#define CADENCE_UART_GET_CLASS(obj) \ + OBJECT_GET_CLASS(CadenceUartClass, (obj), TYPE_CADENCE_UART) + +typedef struct CadenceUartClass { + /*< private >*/ + SysBusDeviceClass parent_class; + + struct ResettablePhases parent_reset_phases; +} CadenceUartClass; + #define UART_SR_INTR_RTRIG 0x00000001 #define UART_SR_INTR_REMPTY 0x00000002 #define UART_SR_INTR_RFUL 0x00000004 @@ -223,6 +235,10 @@ static int uart_can_receive(void *opaque) int ret = MAX(CADENCE_UART_RX_FIFO_SIZE, CADENCE_UART_TX_FIFO_SIZE); uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; + if (device_is_resetting((DeviceState *) opaque)) { + return 0; + } + if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { ret = MIN(ret, CADENCE_UART_RX_FIFO_SIZE - s->rx_count); } @@ -338,6 +354,10 @@ static void uart_receive(void *opaque, const uint8_t *buf, int size) CadenceUARTState *s = opaque; uint32_t ch_mode = s->r[R_MR] & UART_MR_CHMODE; + if (device_is_resetting((DeviceState *) opaque)) { + return; + } + if (ch_mode == NORMAL_MODE || ch_mode == ECHO_MODE) { uart_write_rx_fifo(opaque, buf, size); } @@ -351,6 +371,10 @@ static void uart_event(void *opaque, int event) CadenceUARTState *s = opaque; uint8_t buf = '\0'; + if (device_is_resetting((DeviceState *) opaque)) { + return; + } + if (event == CHR_EVENT_BREAK) { uart_write_rx_fifo(opaque, &buf, 1); } @@ -383,6 +407,10 @@ static void uart_write(void *opaque, hwaddr offset, { CadenceUARTState *s = opaque; + if (device_is_resetting((DeviceState *)opaque)) { + return; + } + DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); offset >>= 2; if (offset >= CADENCE_UART_R_MAX) { @@ -441,6 +469,10 @@ static uint64_t uart_read(void *opaque, hwaddr offset, CadenceUARTState *s = opaque; uint32_t c = 0; + if (device_is_resetting((DeviceState *)opaque)) { + return 0; + } + offset >>= 2; if (offset >= CADENCE_UART_R_MAX) { c = 0; @@ -460,9 +492,14 @@ static const MemoryRegionOps uart_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static void cadence_uart_reset(DeviceState *dev) +static void cadence_uart_reset_init(Object *obj) { - CadenceUARTState *s = CADENCE_UART(dev); + CadenceUARTState *s = CADENCE_UART(obj); + CadenceUartClass *cc = CADENCE_UART_GET_CLASS(obj); + + if (cc->parent_reset_phases.init) { + cc->parent_reset_phases.init(obj); + } s->r[R_CR] = 0x00000128; s->r[R_IMR] = 0; @@ -471,6 +508,28 @@ static void cadence_uart_reset(DeviceState *dev) s->r[R_BRGR] = 0x0000028B; s->r[R_BDIV] = 0x0000000F; s->r[R_TTRIG] = 0x00000020; +} + +static void cadence_uart_reset_hold(Object *obj) +{ + CadenceUARTState *s = CADENCE_UART(obj); + CadenceUartClass *cc = CADENCE_UART_GET_CLASS(obj); + + if (cc->parent_reset_phases.hold) { + cc->parent_reset_phases.hold(obj); + } + + qemu_set_irq(s->irq, 0); +} + +static void cadence_uart_reset_exit(Object *obj) +{ + CadenceUARTState *s = CADENCE_UART(obj); + CadenceUartClass *cc = CADENCE_UART_GET_CLASS(obj); + + if (cc->parent_reset_phases.exit) { + cc->parent_reset_phases.exit(obj); + } uart_rx_reset(s); uart_tx_reset(s); @@ -499,6 +558,8 @@ static void cadence_uart_init(Object *obj) sysbus_init_irq(sbd, &s->irq); s->char_tx_time = (NANOSECONDS_PER_SECOND / 9600) * 10; + + qdev_init_warm_reset_gpio(DEVICE(obj), "rst", DEVICE_RESET_ACTIVE_HIGH); } static int cadence_uart_post_load(void *opaque, int version_id) @@ -544,12 +605,19 @@ static Property cadence_uart_properties[] = { static void cadence_uart_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + CadenceUartClass *cc = CADENCE_UART_CLASS(klass); dc->realize = cadence_uart_realize; dc->vmsd = &vmstate_cadence_uart; - dc->reset = cadence_uart_reset; dc->props = cadence_uart_properties; - } + + resettable_class_set_parent_reset_phases(rc, + cadence_uart_reset_init, + cadence_uart_reset_hold, + cadence_uart_reset_exit, + &cc->parent_reset_phases); +} static const TypeInfo cadence_uart_info = { .name = TYPE_CADENCE_UART, @@ -557,6 +625,7 @@ static const TypeInfo cadence_uart_info = { .instance_size = sizeof(CadenceUARTState), .instance_init = cadence_uart_init, .class_init = cadence_uart_class_init, + .class_size = sizeof(CadenceUartClass), }; static void cadence_uart_register_types(void)