diff mbox series

[PULL,v1,19/38] target-microblaze: dec_msr: Fix MTS to FSR

Message ID 20180529105011.1914-20-edgar.iglesias@gmail.com
State New
Headers show
Series Xilinx queue | expand

Commit Message

Edgar E. Iglesias May 29, 2018, 10:49 a.m. UTC 
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Fix moves to FSR. Not only bit 31 is accessible.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target/microblaze/translate.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 6a270fbece..6f2cafa88a 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -533,11 +533,9 @@  static void dec_msr(DisasContext *dc)
                 break;
             case SR_EAR:
             case SR_ESR:
+            case SR_FSR:
                 tcg_gen_mov_i32(cpu_SR[sr], cpu_R[dc->ra]);
                 break;
-            case 0x7:
-                tcg_gen_andi_i32(cpu_SR[SR_FSR], cpu_R[dc->ra], 31);
-                break;
             case 0x800:
                 tcg_gen_st_i32(cpu_R[dc->ra],
                                cpu_env, offsetof(CPUMBState, slr));