Message ID | 20180508173152.29327-18-edgar.iglesias@gmail.com |
---|---|
State | New |
Headers | show
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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id h2-v6sm3304527ljk.60.2018.05.08.10.32.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 08 May 2018 10:32:19 -0700 (PDT) From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> To: qemu-devel@nongnu.org Date: Tue, 8 May 2018 19:31:33 +0200 Message-Id: <20180508173152.29327-18-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180508173152.29327-1-edgar.iglesias@gmail.com> References: <20180508173152.29327-1-edgar.iglesias@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4010:c07::241 Subject: [Qemu-devel] [PATCH v2 17/36] target-microblaze: dec_msr: Use bool and extract32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, frederic.konrad@adacore.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> |
Series |
target-microblaze: Add support for Extended Addressing
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expand
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diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 4290fb2eaf..0593aff692 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -458,17 +458,20 @@ static void dec_msr(DisasContext *dc) { CPUState *cs = CPU(dc->cpu); TCGv_i32 t0, t1; - unsigned int sr, to, rn; + unsigned int sr, rn; + bool to, clrset; - sr = dc->imm & ((1 << 14) - 1); - to = dc->imm & (1 << 14); + sr = extract32(dc->imm, 0, 14); + to = extract32(dc->imm, 14, 1); + clrset = extract32(dc->imm, 15, 1) == 0; dc->type_b = 1; - if (to) + if (to) { dc->cpustate_changed = 1; + } /* msrclr and msrset. */ - if (!(dc->imm & (1 << 15))) { - unsigned int clr = dc->ir & (1 << 16); + if (clrset) { + bool clr = extract32(dc->ir, 16, 1); LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set", dc->rd, dc->imm);