| Message ID | 20180503115620.10596-2-edgar.iglesias@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | xlnx-zynqmp: Change the Cortex-R5 for Cortex-R5F | expand |
On 05/03/2018 01:56 PM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Add the Cortex-R5F with the optional FPU enabled. > Seems ok to me. Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > target/arm/cpu.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index d175c5e94f..7a7035c037 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1341,6 +1341,14 @@ static void cortex_r5_initfn(Object *obj) > define_arm_cp_regs(cpu, cortexr5_cp_reginfo); > } > > +static void cortex_r5f_initfn(Object *obj) > +{ > + ARMCPU *cpu = ARM_CPU(obj); > + > + cortex_r5_initfn(obj); > + set_feature(&cpu->env, ARM_FEATURE_VFP3); > +} > + > static const ARMCPRegInfo cortexa8_cp_reginfo[] = { > { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, > .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > @@ -1801,6 +1809,7 @@ static const ARMCPUInfo arm_cpus[] = { > { .name = "cortex-m33", .initfn = cortex_m33_initfn, > .class_init = arm_v7m_class_init }, > { .name = "cortex-r5", .initfn = cortex_r5_initfn }, > + { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, > { .name = "cortex-a7", .initfn = cortex_a7_initfn }, > { .name = "cortex-a8", .initfn = cortex_a8_initfn }, > { .name = "cortex-a9", .initfn = cortex_a9_initfn }, >
On Thu, May 3, 2018 at 4:58 AM Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > Add the Cortex-R5F with the optional FPU enabled. > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/arm/cpu.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index d175c5e94f..7a7035c037 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1341,6 +1341,14 @@ static void cortex_r5_initfn(Object *obj) > define_arm_cp_regs(cpu, cortexr5_cp_reginfo); > } > +static void cortex_r5f_initfn(Object *obj) > +{ > + ARMCPU *cpu = ARM_CPU(obj); > + > + cortex_r5_initfn(obj); > + set_feature(&cpu->env, ARM_FEATURE_VFP3); > +} > + > static const ARMCPRegInfo cortexa8_cp_reginfo[] = { > { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, > .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > @@ -1801,6 +1809,7 @@ static const ARMCPUInfo arm_cpus[] = { > { .name = "cortex-m33", .initfn = cortex_m33_initfn, > .class_init = arm_v7m_class_init }, > { .name = "cortex-r5", .initfn = cortex_r5_initfn }, > + { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, > { .name = "cortex-a7", .initfn = cortex_a7_initfn }, > { .name = "cortex-a8", .initfn = cortex_a8_initfn }, > { .name = "cortex-a9", .initfn = cortex_a9_initfn }, > -- > 2.14.1
On 05/03/2018 08:56 AM, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Add the Cortex-R5F with the optional FPU enabled. > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> > --- > target/arm/cpu.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index d175c5e94f..7a7035c037 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1341,6 +1341,14 @@ static void cortex_r5_initfn(Object *obj) > define_arm_cp_regs(cpu, cortexr5_cp_reginfo); > } > > +static void cortex_r5f_initfn(Object *obj) > +{ > + ARMCPU *cpu = ARM_CPU(obj); > + > + cortex_r5_initfn(obj); > + set_feature(&cpu->env, ARM_FEATURE_VFP3); > +} > + > static const ARMCPRegInfo cortexa8_cp_reginfo[] = { > { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, > .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > @@ -1801,6 +1809,7 @@ static const ARMCPUInfo arm_cpus[] = { > { .name = "cortex-m33", .initfn = cortex_m33_initfn, > .class_init = arm_v7m_class_init }, > { .name = "cortex-r5", .initfn = cortex_r5_initfn }, > + { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, > { .name = "cortex-a7", .initfn = cortex_a7_initfn }, > { .name = "cortex-a8", .initfn = cortex_a8_initfn }, > { .name = "cortex-a9", .initfn = cortex_a9_initfn }, >
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d175c5e94f..7a7035c037 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1341,6 +1341,14 @@ static void cortex_r5_initfn(Object *obj) define_arm_cp_regs(cpu, cortexr5_cp_reginfo); } +static void cortex_r5f_initfn(Object *obj) +{ + ARMCPU *cpu = ARM_CPU(obj); + + cortex_r5_initfn(obj); + set_feature(&cpu->env, ARM_FEATURE_VFP3); +} + static const ARMCPRegInfo cortexa8_cp_reginfo[] = { { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, @@ -1801,6 +1809,7 @@ static const ARMCPUInfo arm_cpus[] = { { .name = "cortex-m33", .initfn = cortex_m33_initfn, .class_init = arm_v7m_class_init }, { .name = "cortex-r5", .initfn = cortex_r5_initfn }, + { .name = "cortex-r5f", .initfn = cortex_r5f_initfn }, { .name = "cortex-a7", .initfn = cortex_a7_initfn }, { .name = "cortex-a8", .initfn = cortex_a8_initfn }, { .name = "cortex-a9", .initfn = cortex_a9_initfn },